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UHF ASK/FSK Receiver User's Guide
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ATA8210
ATA8215
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4
Hardware
4.9
AVR Controller
4.9.2
CPU Core
Introduction
Features
1
Quick References
2
General Product Description
3
System Functional Description
4
Hardware
4.1
Overview
4.2
Crystal Oscillator
4.3
Fractional-N PLL
4.4
Receive Path
4.5
Data and Support FIFOs
4.6
SPDT RF Switch
4.7
RF Front-End Register Description
4.8
Sequencer State Machine
4.9
AVR Controller
4.9.1
AVR Controller Sub-System Overview
4.9.2
CPU Core
4.9.2.1
Architectural Overview
4.9.2.2
ALU
4.9.2.3
Status Register
4.9.2.4
General Purpose Register File
4.9.2.5
Stack Pointer
4.9.2.6
Instruction Execution Timing
4.9.2.7
Reset and Interrupt Handling
4.9.3
Memories
4.9.4
System Clock and Clock Options
4.9.5
Sleep Modes and Active Power Reduction
4.9.6
I/O Ports
4.9.7
Timer Module
4.9.8
SPI – Serial Peripheral Interface
4.9.9
CRC
4.9.10
debugWIRE – On-Chip Debug System
4.9.11
Memory Access via SPM/LPM
4.9.12
Memory Programming
4.9.13
Specific Interrupts Handling
4.9.14
External Interrupts
4.10
Power Management
5
Application
6
Timing Characteristics
7
Appendix
8
Document Revision History
Microchip Information
4.9.2 CPU Core
