3.11.8 sEEPromEventConfig eepEventConf
The sEEPromEventConfig eepEventConf variable contains the configuration of the events. For more details on the functional description, see Event Handling from Related Links.
pinEventConf
The pinEventConf variable contains the configuration masks for the wake-up events.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x0094 | pinEventConf | PWRON | — | NPWRON6 | NPWRON5 | NPWRON4 | NPWRON3 | NPWRON2 | NPWRON1 |
Bit 7: PWRON – Event Mask for pin 26/PWRON
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 26 (PWRON)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 26 (PWRON)
Bit 6: Reserved Bits
This bit is reserved for future use and must be set to ‘0’.
Bit 5: NPWRON6 – Event Mask for Pin 29/NPWRON6
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 29 (NPWRON6)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 29 (NPWRON6)
Bit 4: NPWRON5 – Event Mask for Pin 19/NPWRON5
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 19 (NPWRON5)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 19 (NPWRON5)
Bit 3: NPWRON4 – Event Mask for Pin 18/NPWRON4
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 18 (NPWRON4)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 18 (NPWRON4)
Bit 2: NPWRON3 – Event Mask for Pin 17/NPWRON3
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 17 (NPWRON3)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 17 (NPWRON3)
Bit 1: NPWRON2 – Event Mask for Pin16/NPWRON2
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 16 (NPWRON2)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 16 (NPWRON2)
Bit 0: NPWRON1 – Event Mask for Pin 15/NPWRON1
0 = Pin 28/EVENT is NOT set upon a wake check or pin change on pin 15 (NPWRON1)
1 = Pin 28/EVENT is set upon a wake check or pin change on pin 15 (NPWRON1)
sysEventConf
The sysEventConf variable contains the configuration masks for the system events and configuration settings for the RX_ACTIVE and EVENT pins.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x0095 | sysEventConf | SYS_ERR | — | SYS_RDY | AVCCLOW | LOWBATT | RX_ACTIVE_EN | RX_ACTIVE_POL | IRQ_POL |
Bit 7: SYS_ERR – Event Mask for System Error
0 = Pin 28/EVENT is NOT set upon detection of a system error
1 = Pin 28/EVENT is set upon detection of a system error
Bit 6: Reserved Bits
This bit is reserved for future use and must be set to ‘0’.
Bit 5: SYS_RDY – Event Mask for System Ready
0 = Pin 28/EVENT is NOT set after system initialization finishes
1 = Pin 28/EVENT is set after system initialization finishes
Bit 4: AVCCLOW – Event Mask for AVCC Low
0 = Pin 28/EVENT is NOT set if an AVCCLOW interrupt occurs
1 = Pin 28/EVENT is set if an AVCCLOW interrupt occurs
Bit 3: LOWBATT – Event Mask for Low Battery
0 = Pin 28/EVENT is NOT set if a LOWBATT interrupt occurs
1 = Pin 28/EVENT is set if a LOWBATT interrupt occurs
Bit 2: RX_ACTIVE_EN – Enable RX Active signal on pin 29/RX_ACTIVE
0 = The receiver activity is not indicated on pin 29/RX_ACTIVE
1 = The pin 29/RX_ACTIVE is set when the receive path is running and released when the receiver is inactive
Bit 1: RX_ACTIVE_POL – Pin 29/RX_ACTIVE Polarity
0 = Pin 29/RX_ACTIVE is LOW during an active receive path and HIGH during an inactive receive path
1 = Pin 29/RX_ACTIVE is HIGH during an active receive path and LOW during an inactive receive path
Bit 0: IRQ_POL – Pin 28/EVENT Polarity
0 = Pin 28/EVENT is set LOW to indicate an event
1 = PIn 28/EVENT is set HIGH to indicate an event
cmdRdyConf
The cmdRdyConf variable contains the configuration masks for the command ready (CMD_RDY) event.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x0096 | cmdRdyConf | — | TEMP_MEAS | SRC_CAL | FRC_CAL | VCO_CAL | RF_CAL | SELFCHECK | — |
Bit 7: Reserved Bits
This bit is reserved for future use and must be set to ‘0’.
Bit 6: TEMP_MEAS – CMD_RDY Event Mask for Temperature Measurement
0 = Pin 28/EVENT is NOT set after the temperature measurement process finishes
1 = Pin 28/EVENT is set after the temperature measurement process finishes
Bit 5: SRC_CAL – CMD_RDY Event Mask for Polling Cycle/SRC Calibration
0 = Pin 28/EVENT is NOT set after the polling cycle/SRC calibration process finishes
1 = Pin 28/EVENT is set after the polling cycle/SRC calibration process finishes
Bit 4: FRC_CAL – CMD_RDY Event Mask for FRC Calibration
0 = Pin 28/EVENT is NOT set after the FRC calibration process finishes
1 = Pin 28/EVENT is set after the FRC calibration process finishes
Bit 3: VCO_CAL – CMD_RDY Event Mask for VCO Tuning
0 = Pin 28/EVENT is NOT set after the VCO tuning process finishes
1 = Pin 28/EVENT is set after the VCO tuning process finishes
Bit 2: RF_CAL – CMD_RDY Event Mask for RF Calibration
0 = Pin 28/EVENT is NOT set after the RF calibration process finishes
1 = Pin 28/EVENT is set after the RF calibration process finishes
Bit 1: SELFCHECK – CMD_RDY Event Mask for System Self Check and Calibration
0 = Pin 28/EVENT is NOT set after the system self check and calibration process finishes
1 = Pin 28/EVENT is set after the self check and calibration process finishes
Bit 0: Reserved Bits
This bit is reserved for future use and must be set to ‘0’.