3.11.3 sEEPromIOConfig eepio
The sEEPromIOConfig eepio variable contains the initial I/O configuration.
confDDRB, confDDRC
The confDDRB/C variables are a copy of the hardware DDRB/C registers and configure the PORTB and PORTC data direction, respectively. For more details on the functional description, see Initial I/O Port Configuration from Related Links. For more details on the hardware description, see I/O Ports from Related Links.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x000D | confDDRB | DDRB[7:0] | |||||||
0x000E | confDDRC | DDRC[7:0] | |||||||
confMCUCR
The confMCUCR variable is a copy of the microcontroller unit configuration (MCUCR) register and contains various port setting configurations. For more details on the functional description, see Initial I/O Port Configuration from Related Links. For more details on the hardware description, see I/O Ports from Related Links.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x000F | confMCUCR | PB7HS | PB7LS | PB4HS | PUD | ENPS | SPIIO | IVSEL | ÎVCE |
Bit 7: PB7HS – High-Side Driver on Port B7
Bit 6: PB7LS – Low-Side Driver on Port B7
Bit 5: PB4HS – High-Side Driver on Port B4
Bit 4: PUD – Global Pull-Up Resistor Disable
Bit 3: ENPS – Enable Register-Defined Port Settings This bit must always be set to ‘1’.
Bits 2..0: Interrupt Handling
These bits must always be set to ‘0’. The firmware controls the corresponding hardware register bits.
confPCICR
The confPCICR variable is a copy of the pin change interrupt control register (PCICR). For more details on the functional description, see Initial I/O Port Configuration from Related Links. For more details on the hardware description, see Reset and Interrupt Handling from Related Links.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x0010 | confPCICR | — | — | — | — | — | — | PCIE[1:0] | |
Bits 7..2: Reserved Bits
These bits are reserved for future use and must be set to ‘0’.
Bit 1: PCIE1 – Pin Change Interrupt Enable on PORTC
The individual pins must be masked in eepio.confPCMSK1.
Bit 0: PCIE0 – Pin Change Interrupt Enable on PORTB
The individual pins must be masked in eepio.confPCMSK0.
confPCMSK0, confPCMSK1
The confPCMSK0/1 variables are a copy of the pin change mask 0/1 registers (PCMSK0/1). For more details on the functional description, see Initial I/O Port Configuration from Related Links. For more details on the hardware description, see Reset and Interrupt Handling from Related Links.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x0011 | confPCMSK0 | PCMSK0[7:0] | |||||||
0x0012 | confPCMSK1 | PCMSK1[7:0] | |||||||
PCMSK0[7:0]: Pin Change Enable Mask for PORTB
PCMSK1[7:0]: Pin Change Enable Mask for PORTC
confPORTB, confPORTC
The confPORTB/C variables are a copy of the hardware PORTB/C registers and configure the PORTB and PORTC data registers, respectively. For more details on the functional description, see Initial I/O Port Configuration from Related Links. For more details on the hardware description, see I/O Ports from Related Links.
Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
0x0013 | confPORTB | PORTB[7:0] | |||||||
0x0014 | confPORTC | PORTC[7:0] | |||||||