3.2.2.2 FIFO Interrupt Initialization
The support FIFO (SFIFO) and the data FIFO (DFIFO) implement error interrupts for overflow and
underflow events. These interrupts can be switched off by setting the EEPROM variables
eepTrxConf.sysConfig.SFIFO_OFL_UFL_RX_disable and
eepTrxConf.sysConfig.DFIFO_OFL_UFL_RX_disable to ‘1’. See
sEEPromTrxCalib eepTrxCal from Related Links.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0017 | sysConfig | — | — | VS22V | VS5V | SFIFO_OFL_UFL_RX_disable | DFIFO_OFL_UFL_RX_disable | AVCCdisable | LOWBATTdisable |