3.2.2.11 Clock Initialization
If they are not used by at least one module, the FRC and SRC oscillators are automatically switched off by default. This mechanism can be deactivated, if required. The oscillators are, then, running permanently, which can decrease the start-up time from sleep mode. The feature can be activated by the FRC always on (FRCAO) and SRC always on (SRCAO) bits in the EEPROM variable eepTrxConf.clkConfig. See sEEPromTrxConfig eepTrxConf from Related Links.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0015 | clkConfig | — | — | SRCAO | FRCAO | — | CLKOEN | CLKOS[1:0] | |
A system clock can be output on the CLK_OUT pin. Available clock sources are SRC, FRC and XTO. The clock divider must be configured to result in an output clock of less then 4.5 MHz. For more details on electrical characteristics, refer to the ATA8210/ATA8215 UHF ASK/FSK Receiver Data Sheet (9344E), section 4.7, parameter number. 15.90. The firmware initializes the clock output configuration according to the settings in the EEPROM variables eepTrxConfig.clkConfig and eepTrxConfig.clkOutDiv. See sEEPromTrxConfig eepTrxConf from Related Links.
| Address | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|---|---|
| 0x0015 | clkConfig | — | — | SRCAO | FRCAO | — | CLKOEN | CLKOS[1:0] | |
| 0x0018 | clkOutDiv | CLKOD[7:0] | |||||||
|
Note: If the clock output
is enabled, the I/O port configuration of pin PB0 must be set to
output.
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