1.6 Simulation Flow

The following steps describe the simulation flow:

  1. At the start, the transceiver is kept at reset.
  2. Once the device initialization is done, the transceiver is brought out of reset.
  3. Constant K28.5 character is provided to transceiver.
  4. The transmitter lanes are connected to receiver lanes internally in the testbench stimulus.
  5. The transceiver is reconfigured at 1.25G by providing a pulse on Switch_1_25_G signal.
  6. The transceiver is reconfigured at 2.5G by providing a pulse on Switch_2_5_G signal. See Figure 1-11.
  7. The transceiver is reconfigured at 5G by providing a pulse on Switch_5_G signal.
  8. The OUT0 and OUT1 of Dynamic CCC are reconfigured by providing a pulse on Switch_CCC_OUT0_OUT1. See Figure 1-12.
  9. The OUT2 and OUT3 of Dynamic CCC are reconfigured by providing a pulse on Switch_CCC_OUT2_OUT3. See Figure 1-12.
  10. The status signal denotes which reconfiguration is used currently.
Important: When the pulse is provided on Switch_1_25_G, Switch_2_5_G, and Switch_5_G signals, the RX_valid and RX_READY signals are deasserted and asserted once the reconfiguration is complete where as RX_IDLE (active-low) is asserted indicating inactivity on the RX data path and deasserted once the reconfiguration is complete.
Figure 1-10. Top Level Simulation
Figure 1-11. 2.5G Transceiver Simulation
Figure 1-12. CCC Output Frequency Simulation