1.3 Demo Design

The following steps describe the data flow in the demo design:

  1. OSC_160 MHz provides 160 MHz clock source to PF_CCC_50 block and CCC block.
  2. The PF_CCC_50 block provides 50 MHz clock for the fabric.
  3. The 50 MHz fabric clock drives Reset-Synchronizer, CoreABC, and PF_DRI modules.
  4. The transceiver (PF_XVCR) block instantiates the transceiver in 8b10b mode. This block receives clock from the REF_CLK signal of PF_XCVR_REF_CLK_0. The PF_TX_PLL_0 block also derives its reference clock from REF_CLK of PF_XCVR_REF_CLK_0.
  5. The TX and RX lanes of the transceiver are externally looped back using SMA cables.
  6. After CoreABC instruction is executed, the RX_VAL and RX_READY outputs must be monitored for link status.
  7. The Rate_Status block indicates the rate at which the transceiver and the Dynamic CCC are configured.
Figure 1-1. DRI Block Diagram