1.8 Reset Structure

When PLL_LOCK output from CCC_50 block and DEVICE_INIT_DONE signal from PF_INIT_MONITOR block are asserted, the Reset_Synchronizer_0 (CoreReset_PF) module releases active low reset of Soft_Processor_0 (CoreABC), reconfiguration_controller_0 (PF_DRI), and the Rate_status_0 modules.

DEVICE_INIT_DONE signal is asserted when the device initialization is complete. For more information about device initialization, see PolarFire Family Power-Up and Resets User Guide . For more information on CoreReset_PF IP core, see the CoreReset_PF handbook from the Libero catalog.

The following figure shows the reset structure of the design.

Figure 1-14. Reset Structure
Important:
  • The DRI PCLK must be gated off until a valid source clock is present and device initialization is completed. It is recommended to use an RGCLKINT macro when external clock source is used. The gate enable signal must be qualified by the DEVICE_INIT_DONE and AUTO_CALIB_DONE outputs of the PF_INIT_MONITOR IP.
  • In this design, INIT MONITOR and CoreReset_PF are used for stable clock and reset generation.