1.4 Port Description

The following table lists the key signals for this design.

Table 1-2. Port Description
SignalDirectionDescription
REF_CLK_PAD_P and REF_CLK_PAD_N—Differential reference clock is generated from the on-board 125 MHz oscillator
LANE0_RXD_NInputTransceiver receiver differential input
LANE0_RXD_PInputTransceiver receiver differential input
LANE0_TXD_NOutputTransceiver transmitter differential output
LANE0_TXD_POutputTransceiver transmitter differential output
LANE0_RX_READYOutputAsserted when the CDR is phase-locked to the incoming data transitions and the de-serializer is powered-up.
LANE0_TX_CLK_STABLEOutputTransmit transceiver/PCS lane ready flag. This flag is asserted when the transmit PLL is locked to the reference clock.
LANE0_RX_VALOutputRX_VAL indicates that the XCVR data path is initialized.
RX_CLK_ROutputGlobal or regional receive clock to the fabric
TX_CLK_ROutputGlobal or regional transmit clock to the fabric
OUT0_FABCLK_0OutputDynamic CCC OUT0 Fabric Clock
OUT1_FABCLK_0OutputDynamic CCC OUT1 Fabric Clock
OUT2_FABCLK_0OutputDynamic CCC OUT2 Fabric Clock
OUT3_FABCLK_0OutputDynamic CCC OUT3 Fabric Clock