38.1 Module Overview

The CAN module implements several aspects of the CAN protocol:

  1. The Bit Stream Processor (BSP) is an implementation of the Medium Access Control (MAC) of the CAN protocol described in ISO 11898-1. It serializes and deserializes the bit stream, encodes and decodes the CAN frames, manages the medium access, acknowledges frames, and detects and signals errors.
  2. The TX handler prioritizes the messages that are requested for transmission by the transmit FIFOs. It uses the RAM interface to fetch the transmit data from RAM and provides it to the BSP for transmission.
  3. The BSP provides received messages to the RX handler. The RX handler uses an acceptance filter, which filters the messages that are to be stored in the receive FIFOs. It uses the RAM interface to store received data into the RAM.
  4. Each FIFO can be configured either as a transmit or receive FIFO. The FIFO control keeps track of the FIFO head and tail and calculates the user address. In a TX FIFO, the user address points to the address in RAM where the data for the next transmit message is stored. In an RX FIFO, the user address points to the address in RAM where the data of the next receive message will be read. The user notifies the FIFO that a message is written to or read from RAM by incrementing the head/tail of the FIFO.
  5. The TXQ is a special transmit FIFO that transmits the messages, based on the ID of the messages stored in the queue.
  6. The TEF stores the message IDs of the transmitted messages.
  7. A free-running Time Base Counter (TBC) is used to timestamp received messages. Messages in the TEF can also be timestamped.
  8. The CAN controller module generates interrupts when new messages are received or when messages are transmitted successfully.

The CANRX input pin is selected with the CANRXPPS register. The CANTX output pin is selected with each pin’s RxyPPS register.

Note: The CANRX pin defaults to pin RB3, but the CANTX has no default location and must be assigned to a pin before CAN transmissions can occur.

In modes that enable the CANRX pin, the user must ensure that the appropriate TRIS bit for CANRX is set to configure the pin as an input, and the associated ANSEL bit for that pin is cleared to enable the digital input buffer. In addition, in modes that enable the CANTX pin, the appropriate TRIS bit for the associated pin must be cleared to enable pin output.