50.4.2 Internal Oscillator Parameters(1)

Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
OS50FHFOSCPrecision Calibrated HFINTOSC Frequency(2)—

4

8

12

16

32

48

64

—MHz
OS51*FHFOSCLPLow-Power Optimized HFINTOSC Frequency(3)—1—MHzFRQ = 'b0000;
OS51A*—2—MHzFRQ = 'b0001;
OS52FMFOSCInternal Calibrated MFINTOSC Frequency—500—kHz
OS53FLFOSCInternal LFINTOSC Frequency—31—kHz
OS54*THFOSCSTHFINTOSC Wake-up from Sleep Start-up Time—19.0—μsVREGPM = 'b00, System Clock at 4 MHz
OS54A*—30.0—μsVREGPM = 'b01, System Clock at 4 MHz
OS54B*—115—μsVREGPM = 'b10, System Clock at 4 MHz
OS54C*—120—μsVREGPM = 'b11, System Clock at 4 MHz
OS56*TLFOSCSTLFINTOSC Wake-up from Sleep Start-up Time—900—μsVREGPM = 'b1x, System Clock at 31 kHz (LFINTOSC)
OS57%CALOSCTUNE Step Size—0.25—%

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.
  2. See the figure below.
  3. Frequencies are not calibrated.
Figure 50-5. Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature