42.8.7 TWIHS SMBus Timing Register
This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register.
| Name: | TWIHS_SMBTR |
| Offset: | 0x38 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| THMAX[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TLOWM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TLOWS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRESC[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 31:24 – THMAX[7:0] Clock High Maximum Cycles
Clock cycles in clock high maximum count. Prescaled by PRESC. Used for bus free detection. Used to time THIGH:MAX.
Bits 23:16 – TLOWM[7:0] Host Clock Stretch Maximum Cycles
| Value | Description |
|---|---|
| 0 |
TLOW:MEXT timeout check disabled. |
| 1–255 |
Clock cycles in Host maximum clock stretch count. Prescaled by PRESC. Used to time TLOW:MEXT. |
Bits 15:8 – TLOWS[7:0] Client Clock Stretch Maximum Cycles
| Value | Description |
|---|---|
| 0 |
TLOW:SEXT timeout check disabled. |
| 1–255 |
Clock cycles in Client maximum clock stretch count. Prescaled by PRESC. Used to time TLOW:SEXT. |
Bits 3:0 – PRESC[3:0] SMBus Clock Prescaler
Used to specify how to prescale the TLOWS, TLOWM and THMAX counters in SMBTR. Counters are prescaled according to the following formula: