42.8.13 TWIHS SleepWalking Matching Register
This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register.
| Name: | TWIHS_SWMR |
| Offset: | 0x4C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DATAM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SADR3[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SADR2[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SADR1[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 31:24 – DATAM[7:0] Data Match
The TWIHS module extends the SleepWalking matching process to the first received data, comparing it with DATAM if DATAMEN bit is enabled.
Bits 22:16 – SADR3[6:0] Client Address 3
Client address 3. The TWIHS module matches on this additional address if SADR3EN bit is enabled.
Bits 14:8 – SADR2[6:0] Client Address 2
Client address 2. The TWIHS module matches on this additional address if SADR2EN bit is enabled.
Bits 6:0 – SADR1[6:0] Client Address 1
Client address 1. The TWIHS module matches on this additional address if SADR1EN bit is enabled.