42.8.11 TWIHS Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is disabled.

1: The corresponding interrupt is enabled.

Name: TWIHS_IMR
Offset: 0x2C
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   SMBHHMSMBDAMPECERRTOUT MCACK 
Access RRRRR 
Reset 00000 
Bit 15141312111098 
     EOSACCSCL_WSARBLSTNACK 
Access RRRR 
Reset 0000 
Bit 76543210 
 UNREOVREGACCSVACC TXRDYRXRDYTXCOMP 
Access RRRRRRR 
Reset 0000000 

Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt Mask

Bit 20 – SMBDAM SMBus Default Address Match Interrupt Mask

Bit 19 – PECERR PEC Error Interrupt Mask

Bit 18 – TOUT Timeout Error Interrupt Mask

Bit 16 – MCACK Host Code Acknowledge Interrupt Mask

Bit 11 – EOSACC End Of Client Access Interrupt Mask

Bit 10 – SCL_WS Clock Wait State Interrupt Mask

Bit 9 – ARBLST Arbitration Lost Interrupt Mask

Bit 8 – NACK Not Acknowledge Interrupt Mask

Bit 7 – UNRE Underrun Error Interrupt Mask

Bit 6 – OVRE Overrun Error Interrupt Mask

Bit 5 – GACC General Call Access Interrupt Mask

Bit 4 – SVACC Client Access Interrupt Mask

Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Mask

Bit 1 – RXRDY Receive Holding Register Ready Interrupt Mask

Bit 0 – TXCOMP Transmission Completed Interrupt Mask