42.8.5 TWIHS Clock Waveform Generator Register

This register can only be written if the WPEN bit is cleared in the TWIHS Write Protection Mode Register.

TWIHS_CWGR is used in Host mode only.

Name:	TWIHS_CWGR
Offset:	0x10
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
			HOLD[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
						CKDIV[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	15	14	13	12	11	10	9	8
	CHDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CLDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 29:24 – HOLD[5:0] TWD Hold Time Versus TWCK Falling

If High-speed mode is selected TWD is internally modified on the TWCK falling edge to meet the I2C specified maximum hold time, else if High-speed mode is not configured TWD is kept unchanged after TWCK falling edge for a period of (HOLD + 3) × t_{peripheral clock}.

Bits 18:16 – CKDIV[2:0] Clock Divider

The CKDIV is used to increase both SCL high and low periods.

Bits 15:8 – CHDIV[7:0] Clock High Divider

The SCL high period is defined as follows:

t_high = ((CHDIV × 2^CKDIV) + 3) × t_{peripheral clock}

Bits 7:0 – CLDIV[7:0] Clock Low Divider

The SCL low period is defined as follows:

t_low = ((CLDIV × 2^CKDIV) + 3) × t_{peripheral clock}