The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
TWIHS_IDR
Offset:
0x28
Reset:
–
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
SMBHHM
SMBDAM
PECERR
TOUT
MCACK
Access
W
W
W
W
W
Reset
–
–
–
–
–
Bit
15
14
13
12
11
10
9
8
EOSACC
SCL_WS
ARBLST
NACK
Access
W
W
W
W
Reset
–
–
–
–
Bit
7
6
5
4
3
2
1
0
UNRE
OVRE
GACC
SVACC
TXRDY
RXRDY
TXCOMP
Access
W
W
W
W
W
W
W
Reset
–
–
–
–
–
–
–
Bit 21 – SMBHHM SMBus Host Header Address Match Interrupt
Disable
Bit 20 – SMBDAM SMBus Default Address Match Interrupt
Disable
Bit 19 – PECERR PEC Error Interrupt
Disable
Bit 18 – TOUT Timeout Error Interrupt
Disable
Bit 16 – MCACK Host Code Acknowledge Interrupt
Disable
Bit 11 – EOSACC End Of Client Access Interrupt
Disable
Bit 10 – SCL_WS Clock Wait State Interrupt Disable
Bit 9 – ARBLST Arbitration Lost Interrupt Disable
Bit 8 – NACK Not Acknowledge Interrupt Disable
Bit 7 – UNRE Underrun Error Interrupt Disable
Bit 6 – OVRE Overrun Error Interrupt Disable
Bit 5 – GACC General Call Access Interrupt Disable
Bit 4 – SVACC Client Access Interrupt
Disable
Bit 2 – TXRDY Transmit Holding Register Ready Interrupt Disable
Bit 1 – RXRDY Receive Holding Register Ready Interrupt Disable
Bit 0 – TXCOMP Transmission Completed Interrupt Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
