39.14.3 HSMCI Data Timeout Register
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
| Name: | HSMCI_DTOR |
| Offset: | 0x08 |
| Reset: | 0x0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DTOMUL[2:0] | DTOCYC[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:4 – DTOMUL[2:0] Data Timeout Multiplier
If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the HSMCI Status Register (HSMCI_SR) rises.
| Value | Name | Description |
|---|---|---|
| 0 | 1 | DTOCYC |
| 1 | 16 | DTOCYC x 16 |
| 2 | 128 | DTOCYC x 128 |
| 3 | 256 | DTOCYC x 256 |
| 4 | 1024 | DTOCYC x 1024 |
| 5 | 4096 | DTOCYC x 4096 |
| 6 | 65536 | DTOCYC x 65536 |
| 7 | 1048576 | DTOCYC x 1048576 |
Bits 3:0 – DTOCYC[3:0] Data Timeout Cycle Number
This field determines the maximum number of Host Clock cycles that the HSMCI waits between two data block transfers. It equals (DTOCYC x Multiplier).