39.14.13 HSMCI Interrupt Enable Register

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Enables the corresponding interrupt.

Name: HSMCI_IER
Offset: 0x44
Property: Write-only

Bit 3130292827262524 
 UNREOVREACKRCVEACKRCVXFRDONEFIFOEMPTY BLKOVRE 
Access WWWWWWW 
Reset  
Bit 2322212019181716 
 CSTOEDTOEDCRCERTOERENDERCRCERDIRERINDE 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
   CSRCVSDIOWAIT   SDIOIRQA 
Access WWW 
Reset  
Bit 76543210 
   NOTBUSYDTIPBLKETXRDYRXRDYCMDRDY 
Access WWWWWW 
Reset  

Bit 31 – UNRE Underrun Interrupt Enable

Bit 30 – OVRE Overrun Interrupt Enable

Bit 29 – ACKRCVE Boot Acknowledge Error Interrupt Enable

Bit 28 – ACKRCV Boot Acknowledge Interrupt Enable

Bit 27 – XFRDONE Transfer Done Interrupt enable

Bit 26 – FIFOEMPTY FIFO empty Interrupt enable

Bit 24 – BLKOVRE DMA Block Overrun Error Interrupt Enable

Bit 23 – CSTOE Completion Signal Timeout Error Interrupt Enable

Bit 22 – DTOE Data Time-out Error Interrupt Enable

Bit 21 – DCRCE Data CRC Error Interrupt Enable

Bit 20 – RTOE Response Time-out Error Interrupt Enable

Bit 19 – RENDE Response End Bit Error Interrupt Enable

Bit 18 – RCRCE Response CRC Error Interrupt Enable

Bit 17 – RDIRE Response Direction Error Interrupt Enable

Bit 16 – RINDE Response Index Error Interrupt Enable

Bit 13 – CSRCV Completion Signal Received Interrupt Enable

Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable

Bit 8 – SDIOIRQA SDIO Interrupt for Slot A Interrupt Enable

Bit 5 – NOTBUSY Data Not Busy Interrupt Enable

Bit 4 – DTIP Data Transfer in Progress Interrupt Enable

Bit 3 – BLKE Data Block Ended Interrupt Enable

Bit 2 – TXRDY Transmit Ready Interrupt Enable

Bit 1 – RXRDY Receiver Ready Interrupt Enable

Bit 0 – CMDRDY Command Ready Interrupt Enable