39.14.15 HSMCI Interrupt Mask Register

The following configuration values are valid for all listed bit names of this register:

0: The corresponding interrupt is not enabled.

1: The corresponding interrupt is enabled.

Name: HSMCI_IMR
Offset: 0x4C
Reset: 0x0
Property: Read-only

Bit 3130292827262524 
 UNREOVREACKRCVEACKRCVXFRDONEFIFOEMPTY BLKOVRE 
Access RRRRRRR 
Reset 0000000 
Bit 2322212019181716 
 CSTOEDTOEDCRCERTOERENDERCRCERDIRERINDE 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
   CSRCVSDIOWAIT   SDIOIRQA 
Access RRR 
Reset 000 
Bit 76543210 
   NOTBUSYDTIPBLKETXRDYRXRDYCMDRDY 
Access RRRRRR 
Reset 000000 

Bit 31 – UNRE Underrun Interrupt Mask

Bit 30 – OVRE Overrun Interrupt Mask

Bit 29 – ACKRCVE Boot Operation Acknowledge Error Interrupt Mask

Bit 28 – ACKRCV Boot Operation Acknowledge Received Interrupt Mask

Bit 27 – XFRDONE Transfer Done Interrupt Mask

Bit 26 – FIFOEMPTY FIFO Empty Interrupt Mask

Bit 24 – BLKOVRE DMA Block Overrun Error Interrupt Mask

Bit 23 – CSTOE Completion Signal Time-out Error Interrupt Mask

Bit 22 – DTOE Data Time-out Error Interrupt Mask

Bit 21 – DCRCE Data CRC Error Interrupt Mask

Bit 20 – RTOE Response Time-out Error Interrupt Mask

Bit 19 – RENDE Response End Bit Error Interrupt Mask

Bit 18 – RCRCE Response CRC Error Interrupt Mask

Bit 17 – RDIRE Response Direction Error Interrupt Mask

Bit 16 – RINDE Response Index Error Interrupt Mask

Bit 13 – CSRCV Completion Signal Received Interrupt Mask

Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask

Bit 8 – SDIOIRQA SDIO Interrupt for Slot A Interrupt Mask

Bit 5 – NOTBUSY Data Not Busy Interrupt Mask

Bit 4 – DTIP Data Transfer in Progress Interrupt Mask

Bit 3 – BLKE Data Block Ended Interrupt Mask

Bit 2 – TXRDY Transmit Ready Interrupt Mask

Bit 1 – RXRDY Receiver Ready Interrupt Mask

Bit 0 – CMDRDY Command Ready Interrupt Mask