The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Disables the corresponding interrupt.
Name:
HSMCI_IDR
Offset:
0x48
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
UNRE
OVRE
ACKRCVE
ACKRCV
XFRDONE
FIFOEMPTY
BLKOVRE
Access
W
W
W
W
W
W
W
Reset
Bit
23
22
21
20
19
18
17
16
CSTOE
DTOE
DCRCE
RTOE
RENDE
RCRCE
RDIRE
RINDE
Access
W
W
W
W
W
W
W
W
Reset
Bit
15
14
13
12
11
10
9
8
CSRCV
SDIOWAIT
SDIOIRQA
Access
W
W
W
Reset
Bit
7
6
5
4
3
2
1
0
NOTBUSY
DTIP
BLKE
TXRDY
RXRDY
CMDRDY
Access
W
W
W
W
W
W
Reset
Bit 31 – UNRE Underrun Interrupt Disable
Bit 30 – OVRE Overrun Interrupt Disable
Bit 29 – ACKRCVE Boot Acknowledge Error Interrupt Disable
Bit 28 – ACKRCV Boot Acknowledge Interrupt Disable
Bit 27 – XFRDONE Transfer Done Interrupt Disable
Bit 26 – FIFOEMPTY FIFO empty Interrupt Disable
Bit 24 – BLKOVRE DMA Block Overrun Error Interrupt Disable
Bit 23 – CSTOE Completion Signal Time out Error Interrupt Disable
Bit 22 – DTOE Data Time-out Error Interrupt Disable
Bit 21 – DCRCE Data CRC Error Interrupt Disable
Bit 20 – RTOE Response Time-out Error Interrupt Disable
Bit 19 – RENDE Response End Bit Error Interrupt Disable
Bit 18 – RCRCE Response CRC Error Interrupt Disable
Bit 17 – RDIRE Response Direction Error Interrupt Disable
Bit 16 – RINDE Response Index Error Interrupt Disable
Bit 13 – CSRCV Completion Signal received interrupt Disable
Bit 12 – SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable
Bit 8 – SDIOIRQA SDIO Interrupt for Slot A Interrupt Disable
Bit 5 – NOTBUSY Data Not Busy Interrupt Disable
Bit 4 – DTIP Data Transfer in Progress Interrupt Disable
Bit 3 – BLKE Data Block Ended Interrupt Disable
Bit 2 – TXRDY Transmit Ready Interrupt Disable
Bit 1 – RXRDY Receiver Ready Interrupt Disable
Bit 0 – CMDRDY Command Ready Interrupt Disable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
