39.14.12 HSMCI Status Register
| Name: | HSMCI_SR |
| Offset: | 0x40 |
| Reset: | 0xC0E5 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| UNRE | OVRE | ACKRCVE | ACKRCV | XFRDONE | FIFOEMPTY | BLKOVRE | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CSTOE | DTOE | DCRCE | RTOE | RENDE | RCRCE | RDIRE | RINDE | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CSRCV | SDIOWAIT | SDIOIRQA | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NOTBUSY | DTIP | BLKE | TXRDY | RXRDY | CMDRDY | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 1 | 0 | 0 | 1 | 0 | 1 |
Bit 31 – UNRE Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
If FERRCTRL = 1 in HSMCI_CFG, OVRE is cleared on read.
If FERRCTRL = 0 in HSMCI_CFG, OVRE is cleared by writing HSMCI_CMDR.
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | At least one 8-bit data has been sent without valid information (not written). |
Bit 30 – OVRE Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0)
If FERRCTRL = 1 in HSMCI_CFG, OVRE is cleared on read.
If FERRCTRL = 0 in HSMCI_CFG, OVRE is cleared by writing HSMCI_CMDR.
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | At least one 8-bit received data has been lost (not read). |
Bit 29 – ACKRCVE Boot Operation Acknowledge Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No boot operation error since the last read of HSMCI_SR |
| 1 | Corrupted Boot Acknowledge signal received since the last read of HSMCI_SR. |
Bit 28 – ACKRCV Boot Operation Acknowledge Received (cleared on read)
| Value | Description |
|---|---|
| 0 | No Boot acknowledge received since the last read of the HSMCI_SR. |
| 1 | A Boot acknowledge signal has been received since the last read of HSMCI_SR. |
Bit 27 – XFRDONE Transfer Done flag
| Value | Description |
|---|---|
| 0 | A transfer is in progress. |
| 1 | Command Register is ready to operate and the data bus is in the idle state. |
Bit 26 – FIFOEMPTY FIFO empty flag
| Value | Description |
|---|---|
| 0 | FIFO contains at least one byte. |
| 1 | FIFO is empty. |
Bit 24 – BLKOVRE DMA Block Overrun Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | A new block of data is received and the DMA controller has not started to move the current pending block, a block overrun is raised. |
Bit 23 – CSTOE Completion Signal Time-out Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. |
Bit 22 – DTOE Data Time-out Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. |
Bit 21 – DCRCE Data CRC Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | A CRC16 error has been detected in the last data block. |
Bit 20 – RTOE Response Time-out Error (cleared by writing in HSMCI_CMDR)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. |
Bit 19 – RENDE Response End Bit Error (cleared by writing in HSMCI_CMDR)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | The end bit of the response has not been detected. |
Bit 18 – RCRCE Response CRC Error (cleared by writing in HSMCI_CMDR)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | A CRC7 error has been detected in the response. |
Bit 17 – RDIRE Response Direction Error (cleared by writing in HSMCI_CMDR)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | The direction bit from card to host in the response has not been detected. |
Bit 16 – RINDE Response Index Error (cleared by writing in HSMCI_CMDR)
| Value | Description |
|---|---|
| 0 | No error. |
| 1 | A mismatch is detected between the command index sent and the response index received. |
Bit 13 – CSRCV CE-ATA Completion Signal Received (cleared on read)
| Value | Description |
|---|---|
| 0 | No completion signal received since last status read operation. |
| 1 | The device has issued a command completion signal on the command line. |
Bit 12 – SDIOWAIT SDIO Read Wait Operation Status
| Value | Description |
|---|---|
| 0 | Normal Bus operation. |
| 1 | The data bus has entered IO wait state. |
Bit 8 – SDIOIRQA SDIO Interrupt for Slot A (cleared on read)
| Value | Description |
|---|---|
| 0 | No interrupt detected on SDIO Slot A. |
| 1 | An SDIO Interrupt on Slot A occurred. |
Bit 5 – NOTBUSY HSMCI Not Busy
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command. For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command (CMD12).
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with predefined block count, the NOTBUSY flag is set at the end of the last received data block.
The NOTBUSY flag allows to deal with these different states.
| Value | Description |
|---|---|
| 0 | The HSMCI is not ready for new data transfer. Cleared at the end of the card response. |
| 1 | The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. |
Bit 4 – DTIP Data Transfer in Progress (cleared at the end of CRC16 calculation)
| Value | Description |
|---|---|
| 0 | No data transfer in progress. |
| 1 | The current data transfer is still in progress, including CRC16 calculation. |
Bit 3 – BLKE Data Block Ended (cleared on read)
This flag must be used only for Write Operations.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
| Value | Description |
|---|---|
| 0 | A data block transfer is not yet finished. |
| 1 | A data block transfer has ended, including the CRC16 Status transmission. The flag is set for each transmitted CRC Status. |
Bit 2 – TXRDY Transmit Ready (cleared by writing in HSMCI_TDR)
| Value | Description |
|---|---|
| 0 | The last data written in HSMCI_TDR has not yet been transferred in the Shift Register. |
| 1 | The last data written in HSMCI_TDR has been transferred in the Shift Register. |
Bit 1 – RXRDY Receiver Ready (cleared by reading HSMCI_RDR)
| Value | Description |
|---|---|
| 0 | Data has not yet been received since the last read of HSMCI_RDR. |
| 1 | Data has been received since the last read of HSMCI_RDR. |
Bit 0 – CMDRDY Command Ready (cleared by writing in HSMCI_CMDR)
| Value | Description |
|---|---|
| 0 | A command is in progress. |
| 1 | The last command has been sent. |