39.14.16 HSMCI DMA Configuration Register
This register can only be written if the WPEN bit is cleared in the HSMCI Write Protection Mode Register.
| Name: | HSMCI_DMA |
| Offset: | 0x50 |
| Reset: | 0x0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMAEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CHKSIZE[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bit 8 – DMAEN DMA Hardware Handshaking Enable
| Value | Description |
|---|---|
| 0 | DMA interface is disabled. |
| 1 | DMA Interface is enabled. Note: To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed. |
Bits 324:4 – CHKSIZE[320:0] DMA Channel Read and Write Chunk Size
The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted.
| Value | Name | Description |
|---|---|---|
| 0 | 1 | 1 data available |
| 1 | 2 | 2 data available |
| 2 | 4 | 4 data available |
| 3 | 8 | 8 data available |
| 4 | 16 | 16 data available |