8.1 Timing Specifications
The following figures illustrate the timing diagram of the IS2062/64 SoC in I2S and PCM modes.


Note:
- fs: 8, 16, 32, 44.1, 48, 88.2 and 96 kHz.
- SCLK0: 64 x fs / 256 x fs.
- Word length: 16-bit and 24-bit.
The following figure illustrates the audio interface timing diagram.

The following table provides the timing specifications of the audio interface.
Parameter | Symbol | Min. | Typ. | Max. | Unit |
---|---|---|---|---|---|
SCLK0 duty ratio | dSCLK | — | 50 | — | % |
SCLK0 cycle time | tSCLKCY | 50 | — | — | ns |
SCLK0 pulse width high | tSCLKCH | 20 | — | — | ns |
SCLK0 pulse width low | tSCLKCL | 20 | — | — | ns |
RFS0 setup time to SCLK0 rising edge | tRFSSU | 10 | — | — | ns |
RFS0 hold time from SCLK0 rising edge | tRFSH | 10 | — | — | ns |
DR0 hold time from SCLK0 rising edge | tDH | 10 | — | — | ns |
Note: Test Conditions: Slave mode, fs =
48 kHz, 24-bit data and SCLK0 period = 256 fs