8.1 Timing Specifications

The following figures illustrate the timing diagram of the IS2062/64 SoC in I2S and PCM modes.

Figure 8-1. TIMING DIAGRAM FOR I2S MODES (MASTER/SLAVE)
Figure 8-2. TIMING DIAGRAM FOR PCM MODES (MASTER/SLAVE)
Note:
  1. fs: 8, 16, 32, 44.1, 48, 88.2 and 96 kHz.
  2. SCLK0: 64 x fs / 256 x fs.
  3. Word length: 16-bit and 24-bit.

The following figure illustrates the audio interface timing diagram.

Figure 8-3. AUDIO INTERFACE TIMING

The following table provides the timing specifications of the audio interface.

Table 8-14. AUDIO INTERFACE TIMING SPECIFICATIONS
ParameterSymbolMin.Typ.Max.Unit
SCLK0 duty ratiodSCLK—50—%
SCLK0 cycle timetSCLKCY50——ns
SCLK0 pulse width hightSCLKCH20——ns
SCLK0 pulse width lowtSCLKCL20——ns
RFS0 setup time to SCLK0 rising edgetRFSSU10——ns
RFS0 hold time from SCLK0 rising edgetRFSH10——ns
DR0 hold time from SCLK0 rising edgetDH10——ns
Note: Test Conditions: Slave mode, fs = 48 kHz, 24-bit data and SCLK0 period = 256 fs