1.3 Details on Individual Family Members

The devices of the PIC16(L)F184XX family described in the current data sheet are available in 14/20-pin packages. The block diagram for this device is shown in Figure 1-1.

The devices have the following differences:

Program Flash Memory.
Data Memory SRAM.
Data Memory EEPROM.
A/D channels.
I/O ports.
Enhanced USART.
Input Voltage Range/Power Consumption.

All other features for devices in this family are identical. These are summarized in the following “Device Features” table.

The pinouts for all devices are listed in the pin summary tables.

Table 1-1. Device Features
Features	PIC16(L)F18425	PIC16(L)F18445
Program Memory (KBytes)	14	14
Program Memory (Instructions)	8192	8192
Data Memory (Bytes)	1024	1024
Data EEPROM Memory (Bytes)	256	256
Packages	14 - PDIP 14 - SOIC (3.9 mm) 14 - TSSOP 16 - UQFN (4x4)	20 - PDIP 20 - SOIC (7.5 mm) 20 - SSOP 20 - UQFN (4x4)
I/O Ports	A, C	A, B, C
Capture/Compare/PWM Modules (CCP)	4	4
Configurable Logic Cell (CLC)	4	4
10-Bit Pulse-Width Modulator (PWM)	2	2
12-Bit Analog-to-Digital Module (ADC²) with Computation Accelerator	11 channels	17 channels
5-Bit Digital-to-Analog Module (DAC)	1	1
Comparators	2	2
Numerical Contolled Oscillator (NCO)	1	1
Interrupt Sources	40	40
Timers (16-/8-bit)	4	4
Serial Communications	2 MSSP 1 EUSART	2 MSSP 1 EUSART
Complementary Waveform Generator (CWG)	2	2
Zero-Cross Detect (ZCD)	1	1
Data Signal Modulator (DSM)	1	1
Reference Clock Output Module	1	1
Peripheral Pin Select (PPS)	YES	YES
Peripheral Module Disable (PMD)	YES	YES
Programmable Brown-out Reset (BOR)	YES	YES
Resets (and Delays)	POR, BOR, `RESET` Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT	POR, BOR, `RESET` Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT
Instruction Set	50 instructions 16-levels hardware stack	50 instructions 16-levels hardware stack
Operating Frequency	DC – 32 MHz	DC – 32 MHz

Figure 1-1. PIC16(L)F18425/45 Device Block Diagram

PIC16(L)F18425/45

1.3 Details on Individual Family Members