29.2.1 SPI Host Mode

The host can initiate the data transfer at any time because it controls the SCK line. The host determines when the client (Processor 2, Figure 29-3) is to broadcast data by the software protocol.

In Host mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output can be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register and the corresponding interrupt and Status bits are set.

The clock polarity is selected by appropriately programming the CKP and CKE bits. Then, this will give waveforms for SPI communication as shown in Figure 29-4, Figure 29-6, Figure 29-7 and Figure 29-8, where the MSB is transmitted first. In Host mode, the SPI clock rate (bit rate) is user programmable to be one of the following:

  • FOSC/4 (or TCY)
  • FOSC/16 (or 4 * TCY)
  • FOSC/64 (or 16 * TCY)
  • Timer2 output/2
  • FOSC/(4 * (SSPxADD + 1))

Figure 29-4 shows the waveforms for Host mode.

When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when SSPxBUF is loaded with the received data is shown.

Important: In Host mode, the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPxCLKPPS register. The pin that is selected using the SSPxCLKPPS register must also be made a digital I/O. This is done by clearing the corresponding ANSEL bit.
Figure 29-4. SPI Mode Waveform (Host Mode)