29.1.1 SPI Mode Registers

The MSSP module has five registers accessible for SPI mode operation. These are:

• MSSP STATUS register (SSPxSTAT)
• MSSP Control register 1 (SSPxCON1)
• MSSP Control register 3 (SSPxCON3)
• MSSP Data Buffer register (SSPxBUF)
• MSSP Address register (SSPxADD)
• MSSP Shift register (SSPSR) (Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and STATUS registers for SPI mode operation. The SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write.

One of the five SPI Host modes uses the SSPxADD value to determine the Baud Rate Generator clock frequency. More information on the Baud Rate Generator is available in 29.7 Baud Rate Generator.

SSPSR is the Shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read.

In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.

During transmission, SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR.