16.1 PPS Inputs
Each peripheral has a PPS register with which the input pin to the peripheral is selected. Although each peripheral has its own PPS input selection register, the selections are identical for every peripheral, as shown in xxxPPS. Not all ports are available for input, as shown in Table 16-1.
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.
Input Signal Name | Input Register Name | Default Location at POR (14/16-pin devices) | Reset Value (xxxPPS[4:0]) 14/16-pin devices | Default Location at POR (20-pin devices) | Reset Value (xxxPPS[4:0]) 20-pin devices | PORT From Which Input Is Available | ||
---|---|---|---|---|---|---|---|---|
INT | INTPPS | RA2 | 00010 | RA2 | 00010 | A | B | — |
T0CKI | T0CKIPPS | RA2 | 00010 | RA2 | 00010 | A | B | — |
T1CKI | T1CKIPPS | RA5 | 00101 | RA5 | 00101 | A | — | C |
T1G | T1GPPS | RA4 | 00100 | RA4 | 00100 | — | B | C |
T2IN | T2INPPS | RA5 | 00101 | RA5 | 00101 | A | — | C |
T3CKI | T3CKIPPS | RC5 | 10101 | RC5 | 10101 | — | B | C |
T3G | T3GPPS | RC4 | 10100 | RC4 | 10100 | A | — | C |
T4IN | T4INPPS | RC1 | 10001 | RC1 | 10001 | — | B | C |
T5CKI | T5CKIPPS | RC0 | 10000 | RC0 | 10000 | A | — | C |
T5G | T5GPPS | RC3 | 10011 | RC3 | 10011 | — | B | C |
T6IN | T6INPPS | RC2 | 10010 | RC2 | 10010 | — | B | C |
MDCARL | MDCARLPPS | RC2 | 10010 | RC2 | 10010 | A | — | C |
MDCARH | MDCARHPPS | RC5 | 10101 | RC5 | 10101 | A | — | C |
MDSRC | MDSRCPPS | RA1 | 00001 | RA1 | 00001 | A | — | C |
CCP1IN | CCP1INPPS | RC5 | 10101 | RC5 | 10101 | — | B | C |
CCP2IN | CCP2INPPS | RC3 | 10011 | RC3 | 10011 | — | B | C |
CCP3IN | CCP3INPPS | RA2 | 00010 | RA2 | 00010 | — | B | C |
CCP4IN | CCP4INPPS | RA4 | 00100 | RA4 | 00100 | — | B | C |
CWG1IN | CWG1INPPS | RA2 | 00010 | RA2 | 00010 | — | B | C |
CWG2IN | CWG2INPPS | RA2 | 00010 | RA2 | 00010 | — | B | C |
CLCIN0 | CLCIN0PPS | RC3 | 10011 | RA2 | 00010 | A | — | C |
CLCIN1 | CLCIN1PPS | RC4 | 10100 | RC3 | 10011 | A | — | C |
CLCIN2 | CLCIN2PPS | RC1 | 10001 | RB4 | 01100 | — | B | C |
CLCIN3 | CLCIN3PPS | RA5 | 00101 | RB5 | 01101 | — | B | C |
ADACT | ADACTPPS | RC2 | 10010 | RC2 | 10010 | — | B | C |
SCL1/SCK1 | SSP1CLKPPS | RC0(1) | 10000 | RB6(1) | 01110 | — | B | C |
SDA1/SDI1 | SSP1DATPPS | RC1(1) | 10001 | RB4(1) | 01100 | — | B | C |
SS1 | SS1PPS | RC3 | 10011 | RC6 | 10110 | A | — | C |
SCL2/SCK2 | SSP2CLKPPS | RC4(1) | 10100 | RB7(1) | 01111 | — | B | C |
SDA2/SDI2 | SSP2DATPPS | RC5(1) | 10101 | RB5(1) | 01101 | — | B | C |
SS2 | SS2PPS | RA0 | 00000 | RA1 | 00001 | — | B | C |
RX1/DT1 | RX1PPS | RC5 | 10101 | RB5 | 01101 | — | B | C |
TX1/CK1 | CK1PPS | RC4 | 10100 | RB7 | 01111 | — | B | C |
SMT1SIG | SMT1SIGPPS | RC0 | 10000 | RC0 | 10000 | — | B | C |
SMT1WIN | SMT1WINPPS | RA5 | 00101 | RA5 | 00101 | — | B | C |
- Some pads are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.
Desired Input Pin | Value to Write to Register |
---|---|
RC7 | 01 0111 |
RC6 | 01 0110 |
RC5 | 01 0101 |
RC4 | 01 0100 |
RC3 | 01 0011 |
RC2 | 01 0010 |
RC1 | 01 0001 |
RC0 | 01 0000 |
RB7 | 00 1111 |
RB6 | 00 1110 |
RB5 | 00 1101 |
RB4 | 00 1100 |
RA5 | 00 0101 |
RA4 | 00 0100 |
RA3 | 00 0011 |
RA2 | 00 0010 |
RA1 | 00 0001 |
RA0 | 00 0000 |