12.5.2 CPUDOZE

Doze and Idle Register

Note:
  1. See the link below for more details.
Name: CPUDOZE
Offset: 0x88C

Bit 76543210 
 IDLENDOZENROIDOE DOZE[2:0] 
Access R/WR/W/HC/HSR/WR/W/HC/HSR/WR/WR/W 
Reset 0000000 

Bit 7 – IDLEN Idle Enable bit

ValueDescription
1

A SLEEP instruction places device into Idle mode
0

A SLEEP instruction places the device into Sleep mode

Bit 6 – DOZEN  Doze Enable bit(1)

ValueDescription
1

Places devices into Doze setting
0

Places devices into Normal mode

Bit 5 – ROI  Recover-on-Interrupt bit(1)

ValueDescription
1

Entering the Interrupt Service Routine (ISR) makes DOZEN = 0
0

Entering the Interrupt Service Routine (ISR) does not change DOZEN

Bit 4 – DOE  Doze-on-Exit bit(1)

ValueDescription
1

Executing the ISR makes DOZEN = 1
0

Exiting the ISR does not change DOZEN

Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

ValueDescription
111

1:256
110

1:128
101

1:64
100

1:32
011

1:16
010

1:8
001

1:4
000

1:2
See the link below for more details.