20.6.8 Peripheral BUS Clock Enable Mask3 Register

Note: AHB = Advanced High-performance Bus

APB = Advanced Peripheral Bus

Table 20-9. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CLKMSK3
Offset:	0x48
Reset:	0x0007_FFFF
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					MSK19	MSK18	MSK17	MSK16
Access					R/W	R/W	R/W	R/W
Reset					1	1	1	1


Bit	15	14	13	12	11	10	9	8
	MSK15	MSK14	MSK13	MSK12	MSK11	MSK10	MSK9	MSK8
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	MSK7	MSK6	MSK5	MSK4	MSK3	MSK2	MSK1	MSK0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 – MSKn Clock Enable Mask n


Bit Number	Module
0	SERCOM4
1	SERCOM5
2	SERCOM6
3	SERCOM7
4	TCC4
5	TCC5
6	TCC6
7	TCC7
8	ADC
9	AC
10	PTC
11	I2S
12	PCC
13	CCL
14	PDEC
15	ETH
16	TRNG
17	USB
18	EBI
19	BSDAP

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