20.6.7 Peripheral BUS Clock Enable Mask2 Register
Note: AHB = Advanced High-performance
Bus
APB = Advanced Peripheral Bus
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CLKMSK2 |
| Offset: | 0x44 |
| Reset: | 0x0000_7FFF |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MSK14 | MSK13 | MSK12 | MSK11 | MSK10 | MSK9 | MSK8 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSK7 | MSK6 | MSK5 | MSK4 | MSK2 | MSK1 | MSK0 | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bits 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – MSKn Clock Enable Mask n
Bits 0, 1, 2 – MSKn Clock Enable Mask n
| Bit Number | Module |
|---|---|
| 0 | PORT |
| 1 | DMA0 |
| 2 | DMA1 |
| 4 | PRM |
| 5 | IDAU |
| 6 | EVSYS |
| 7 | SERCOM0 |
| 8 | SERCOM1 |
| 9 | SERCOM2 |
| 10 | SERCOM3 |
| 11 | TCC0 |
| 12 | TCC1 |
| 13 | TCC2 |
| 14 | TCC3 |