3.1.2 Receive

The following IPs form the receive part of the design:

  1. CoreJESD204BRX—This is the receiver interface of the JEDEC JESD204B standard. For the SMA-based loopback design, the Core Configuration of this IP core is as follows:
    • Decoder: Removed
    • Data Width: 32
    • Serdes Mode: 1
    • Scrambling: Disabled
    • Device Subclass Version: Subclass 0
    • JESD204 version: JESD204B
    • No. of Lanes (L+1): 1
    • Checksum calculation type: Octet
    • Frame Alignment Correction: Enabled
    • Link Configuration Error: Enabled
    • RAM Implementation: In FPGA Fabric

    The CoreJESD204BRX and CoreJESD204BTX IPs have the same Link configuration. For more information about CoreJESD204BRX, see CoreJESD204BRX Handbook from Libero SoC catalog.

  2. prbs_checker_0— This block receives the 64-bit data from the CoreJESD204BRX IP core and checks if the received data is correct. It generates an error count and a status signal, which are sent to the GUI for status indication. The data checker checks only the PRBS sequences of the data generator.
  3. LED_DEBUG_BLK_0— This block debug the JESD204B link status and other errors. When the link is up, LEDs 4, 5, 6, 7, 8, 9 glow and LEDs 10 and 11 does not glow (with DIP 1, 2, 3, and 4 set low on the SW11 dip slide switch).

There are two instances of PF_TPSRAM blocks, the PF_TPSRAM_C0_0 block stores the JESD204B link status before sending it to the GUI. The PF_TPSRAM_C1_0 block stores the data received from the CoreJESD204BRX before sending the data to the GUI.

PF_INIT_MONITOR and CoreReset_PF IPs handle the reset mechanism as summarized in the following points.

  • When the DEVICE_INIT_DONE signal from Init_monitor block goes high, the transceiver is completely configured.
  • CoreReset_PF synchronizes resets to the respective user-specified clock domain. This ensures that when the assertion is asynchronous, the deassertion is synchronous to the clock.

The following table lists the important I/O signals of the JESD204B design.

Table 3-1. I/O Signals of the JESD204B Design
SignalDescription
Input Signals
LANE0_RXD_P and LANE0_RXD_NReceiver differential inputs of the transceiver
ARST_NReset signal obtained from the SW6 push button switch on the board
RXReceiver of UART interface
REF_CLK_PAD_P_0 and REF_CLK_PAD_N_0Differential reference clock obtained from the on-board 156.25 MHz oscillator
SEL_IN[3:0]Signal mapped to DIPs 1, 2, 3, and 4 of SW11 dip slide switch used to debug the status and errors
Output Signals
LANE0_TXD_P and LANE0_TXD_NTransmitter differential outputs of the transceiver
LED_OUT[7:0]LEDs 4, 5, 6, 7, 8, 9, 10, and 11 on the board that indicate whether link is up or down
TXTransmitter of the UART interface