1.1.2 Power Supply Sequencing

On detection of a power-up event, the POR circuit sends the power-on reset signal to the system controller and reset controller in the SmartFusion2/IGLOO2 devices. The power-on reset circuitry in SmartFusion2/IGLOO2 devices require the VDD and VPP supplies to ramp monotonically from 0V to the minimum recommended operating voltage within a predefined time. There is no sequencing requirement on VDD and VPP. Four ramp rate options are available during design generation: 50 µs, 1 ms, 10 ms, and 100 ms. Each selection represents the maximum ramp rate to apply to VDD and VPP. The ramp rates can be configured by using the Libero software.

The SERDES_VDD pins are shorted to VDD on silicon die; therefore, Microchip recommends using the same regulator to power up the VDD, SERDES_VDD and SERDES_VDDAIO pins. These three voltage supplies must be powered at the same voltage and must be ramped up and ramped down at the same time.

For information about the power-up to functional time sequence, see DS0128: IGLOO2 and SmartFusion2 Datasheet .

SmartFusion2 and IGLOO2 FPGAs do not have internal brown-out detection and protection circuitry. As described in section Brownout Detection (BOD) of this document, VDD of the FPGA must be protected from any brown-out conditions. You must follow one of the following recommendations during the power-down of the SmartFusion2/IGLOO2 FPGAs:
  • The DEVRSTn pin of the FPGA is asserted (low) once VDD drops below the recommended operating levels.
  • Or VPP rail is powered down before VDD. The VPP voltage level must drop to less than 1V before VDD can start its power-down.

If neither of the previous recommendations are followed during power-down, the FPGA device might experience malfunction that might result in partial or full erasure of user data in the eNVM.