2.19.2 SERCOM LIN Adding Additional Delay Between Break and Sync Bits

In SERCOM USART LIN Host Mode (CTRLA.FORM=0x2), in the case where break, sync and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD=0x2), the LIN Host Header delay between the sync and the ID transmission fields is not correct for the following cases:

  • CTRLC.HDRDLY=0x2, where the delay between sync and ID transmission fields is 8-bit time instead of 4-bit time.
  • CTRLC.HDRDLY=0x3, where the delay between sync and ID transmission fields is 14-bit time instead of 4-bit time.

Work Around:

None

Affected Silicon Revisions

PIC32CX1012BZ25048/WBZ451/WBZ451H
A0A2
XX
PIC32CX1012BZ24032/WBZ450
A2
X