25.8.7 Quick Start Guide for Using DMA with TCC

The supported board list:

  • SAM D21/R21/L21/L22/DA1/C21 Xplained Pro

In this use case, the TCC will be used to generate a PWM signal. Here the pulse width varies through following values with the help of DMA transfer: one quarter of the period, half of the period, and three quarters of the period. The PWM output can be used to drive an LED. The waveform can also be viewed using an oscilloscope. The output signal is also fed back to another TCC channel by event system, the event stamps are captured and transferred to a buffer by DMA.

The PWM output is set up as follows:

Board

Pin

Connect to

SAMD21 Xpro

PB30

LED0

SAMR21 Xpro

PA19

LED0

SAML21 Xpro

PB10

LED0

SAML22 Xpro

PC27

LED0

SAMDA1 Xpro

PB30

LED0

SAMC21 Xpro

PA15

LED0

The TCC module will be setup as follows:

  • GCLK generator 0 (GCLK main) clock source

  • Use double buffering write when set top, compare, or pattern through API

  • No dithering on the counter or compare

  • Prescaler is set to 1024

  • Single Slope PWM wave generation

  • GCLK reload action

  • Don't run in standby

  • No fault or waveform extensions

  • No inversion of waveform output

  • No capture enabled

  • Count upward

  • Don't perform one-shot operations

  • Counter starts on 0

  • Counter top set to 0x1000

  • Channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is set to compare and match value 0x1000*3/4 and generate event

  • Channel 1 is set to capture on input event

The event resource of EVSYS module will be setup as follows:

  • TCC match capture channel 0 (on SAM D21 Xpro) or 3 (on SAM R21 Xpro) is selected as event generator

  • Event generation is synchronous, with rising edge detected

  • TCC match capture channel 1 is the event user

The DMA resource of DMAC module will be setup as follows:

  • Two DMA resources are used

  • Both DMA resources use peripheral trigger

  • Both DMA resources perform beat transfer on trigger

  • Both DMA resources use beat size of 16 bits

  • Both DMA resources are configured to transfer three beats and then repeat again in same buffer

  • On DMA resource which controls the compare value

    • TCC0 overflow triggers DMA transfer

    • The source address increment is enabled

    • The destination address is fixed to TCC channel 0 Compare/Capture register

  • On DMA resource which reads the captured value

    • TCC0 capture on channel 1 triggers DMA transfer

    • The source address is fixed to TCC channel 1 Compare/Capture register

    • The destination address increment is enabled

    • The captured value is transferred to an array in SRAM