5.9 RESET

RESET is an active-high push-pull output and is asserted high when /MR is set to a logic low or the SNS voltage decreases below the threshold voltage. RESET will remain high for the programmed reset timeout delay after SNS > (V_TH + V_HYST) and /MR is set to a logic high, and then RESET will transition low to indicate normal regulation. See the Timing Diagrams section for more information.