32.3.3.4 Output Formats

The output from an ADC conversion is given by the following equations:

Equation 32-1. Single-Ended 10-bit Conversion

{RES}_{} = \frac{V_{I N P}}{V_{R E F}} * 1024 {R E S \in ℤ : 0 \leq R E S \leq 1023}

Equation 32-2. Single-Ended 8-bit Conversion

{RES}_{} = \frac{V_{I N P}}{V_{R E F}} * 256 {R E S \in ℤ : 0 \leq R E S \leq 255}

Where V_INP is the positive input to the ADC, RES is the conversion result, and V_REF is the selected voltage reference.

The ADC has two output registers, the Sample (ADCn.SAMPLE) and Result (ADCn.RESULT) registers. The 16-bit Sample register will always be updated with the latest ADC conversion output (one sample). All accumulation modes will accumulate samples in an internal sample accumulator, configured by the Sample Accumulation Number Select (SAMPNUM) bit field in the Control F (ADCn.CTRLF) register. The sample accumulator is sufficiently wide to avoid overflow for all supported accumulation configurations. The accumulated result will automatically be transferred to the 16-bit Result register at the end of a Burst or Series mode accumulation. In single conversion modes, the Result register will be updated with the latest sample, identical to the Sample (ADCn.SAMPLE) register.

The Left Adjust (LEFTADJ) bit in the Control F (ADCn.CTRLF) register enables left shift of the output data in the modes where this is supported. If enabled, this will left shift the output from both the Result (ADCn.RESULT) and the Sample (ADCn.SAMPLE) registers.

The data format for a sample is an unsigned number, where 0x000 represents zero, and 0x3FF represents the largest number (full scale). If the analog input is higher than the reference level of the ADC, the 10-bit ADC output will be equal to the maximum value of 0x3FF. Likewise, if the input is below 0V, the ADC output will be 0x000.

The following table shows the Result register output formats by mode of operation and left adjustment.

Table 32-3. RESULT Register
MODE	LEFTADJ	RES[15:12]	RES[11:8]	RES[7:0]
`0`	X⁽¹⁾	`0x00`		Conversion[7:0]
`1`	0	`0x00`	Conversion[9:0]
`1`	1	Conversion[9:0] << 4
`2`, `3`	X⁽¹⁾	Accumulation[15:0]

Note:

Left adjust is not available in 8-bit mode or accumulation modes.

The following table shows the Sample register output formats by mode of operation and left adjustment.

Table 32-4. SAMPLE Register
MODE	LEFTADJ	SAMPLE[15:12]	SAMPLE[11:8]	SAMPLE[7:0]
`0`	X	`0x00`		Conversion[7:0]
`0`	X	Sign extension		Signed conversion[7:0]
`Other`	0	`0x00`	Conversion[9:0]
	0	Sign extension	Signed conversion[9:0]
	1	Conversion[9:0] << 4
	1	Signed conversion[9:0] << 4