32.3.3.5 ADC Clock

The ADC clock (CLK_ADC) is scaled down from the peripheral clock (CLK_PER). This can be configured by the Prescaler (PRESC) bit field in the Control B (ADCn.CTRLB) register. The limitations of the ADC Conversion Timing Specifications in the ADC section of the Electrical Characteristics apply.

Some of the internal timings in the ADC are independent of CLK_ADC. To ensure correct internal timing regardless of the ADC clock frequency, a 1 µs timebase, given in CLK_PER cycles, must be written in the TIMEBASE register in the Clock Controller (CLKCTRL) peripheral. Refer to the TIMEBASE register description in the CLKCTRL section for details.

Round up the timebase to the closest integer. The following code snippet shows how to do this using the ceil function.

#include <math.h>
        #define CLK_PER 3333333ul // 20 MHz/6 = 3.333333 MHz
        #define TIMEBASE_VALUE ((uint8_t) ceil(CLK_PER*0.000001))