32.3.3.7 Conversion Timing

Some of the analog modules in the ADC are disabled between conversions and require time to initialize before conversion starts. Only the modules used by the current ADC configuration are enabled, and as the initializations run in parallel, the limiting factor is the module with the slowest initialization time. The following table shows the different initialization times needed by the analog modules.

Table 32-5. ADC Initialization Timing
Analog Module	LOWLAT	Initialization Time (µs)
ADC	`0`	6
ADC	`1`⁽²⁾	0
Settling of internal references	`0`	40
Settling of internal references	`1`⁽²⁾	2⁽¹⁾
Settling internal Temperature Sensor input	`0`	40
Settling internal Temperature Sensor input	`1`⁽²⁾	0
Settling of internal Analog Comparator Reference DAC input	`N/A`	20

Note:

The 2 µs timing is when changing from one internal reference voltage to another internal reference voltage. If changing from a non-internal reference to an internal reference, the full 40 µs delay will be used.
The LOWLAT timing values are valid between two conversions that both have the LOWLAT bit written to ‘1’.

Example: Selecting Tempsense as input and using V_DD as the reference will give a 40 µs initialization time. Using the Tempsense with the 1.024V internal reference will result in a 40 µs initialization time.

The ADC can be put in Low-Latency mode by writing a ‘1’ to the LOWLAT bit in the Control A (ADCn.CTRLA) register. This will keep the configured modules continuously enabled, effectively removing all initialization time at the start of a conversion. The initialization time is still needed when enabling the ADC for the first time and reconfiguring the ADC to use an input or reference that requires initialization, as shown in the table above. The ADC Busy (ADCBUSY) bit in the Status (ADCn.STATUS) register can be used to check if initialization is ongoing.

The sampling period of the input to the ADC is configured through the Sample Duration (SAMPDUR) bit field in the Control E (ADCn.CTRLE) register as (SAMPDUR + ½) CLK_ADC cycles.

If required by the input signal characteristics, SAMPDUR can be increased.

If an internal reference is used, the value of the SAMPDUR bit field in the Control E (ADCn.CTRLE) register must be ≥ 4 µs * f_{CLK_ADC}.

The internal reference has an offset cancellation mechanism with a limited hold time. Offset cancellation is performed at the start of every conversion and is valid for the threshold afterward. The customer should ensure that his conversion has been completed before the threshold has expired by appropriate selection of ADC clock frequency and SAMPDUR. Refer to the Electrical Characteristics for the value of the threshold.