39.10.6 System Clock

Table 39-14. System Clock Timing Characteristics
Symbol	Description	Min.	Typ. ✝	Max.	Unit
f_{CLK_MAIN}^(1,2)	Main clock frequency	—	—	24	MHz
f_CY	Instruction clock frequency	—	f_{CLK_MAIN}	—	MHz
T_CY⁽³⁾	Instruction period	41.6	1/f_CY	—	ns
✝ Data found in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. Note: The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section. The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in the Standard Operating Conditions section. The Instruction Cycle Period (T_CY) is identical to the input oscillator time base period. Exceeding these limits may result in incorrect code execution and/or higher- than-expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. When using an external clock input, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.

f_{CLK_MAIN}^(1,2)

Main clock frequency

—

24

MHz

f_CY

Instruction clock frequency

—

f_{CLK_MAIN}

—

MHz

T_CY⁽³⁾

Instruction period

41.6

1/f_CY

—

ns

✝ Data found in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:

The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section.
The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in the Standard Operating Conditions section.
The Instruction Cycle Period (T_CY) is identical to the input oscillator time base period. Exceeding these limits may result in incorrect code execution and/or higher- than-expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. When using an external clock input, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.