8.3 SDIO Client Interface
The SDIO interface is enabled by connecting the SDIO_SPI_CFG pin to the ground. This SDIO interface is used to exchange the control and 802.11 data. The SDIO interface is available after reset when pin 10 (SDIO_SPI_CFG) is connected to the ground.
This SDIO is a full-speed interface. The interface supports the 1-bit/4-bit SD transfer mode at the clock range of 0-50 MHz. The host uses this interface to read and write from any register within the chip and also configures this module for DMA data transfer.
The SDIO interface pin mapping configuration is provided in the following table.
| Pin # | SDIO Function |
|---|---|
| 10 | SDIO_SPI_CFG: Must be connected to the ground |
| 14 | DAT3: Data 3 |
| 15 | DAT2: Data 2 |
| 16 | DAT1: Data 1 |
| 17 | DAT0: Data 0 |
| 18 | CMD: Command |
| 19 | CLK: Clock |
The SDIO card is detected when it is inserted into an SDIO host. During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO device. The host software obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into the card.
The SD memory card communication is based on an advanced 9-pin interface (clock, command, four data and three power lines) designed to operate at a maximum operating frequency of 50 MHz.