8.4 UART Debug Interface

This module has a Universal Asynchronous Receiver/Transmitter (UART) interface on the J25 (RXD) and J27 (TXD) pins. This interface is intended to be used only for debugging purposes. The UART is compatible with the RS-232 standard, where ATWILC1000-MR110xB operates as Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface.

The following is the default configuration for the UART interface of ATWILC1000-MR110xB:
  • Baud rate: 115200
  • Data: 8 bit
  • Parity: None
  • Stop bit: 1 bit
  • Flow control: None

It also has RX and TX FIFOs, which ensure reliable high-speed reception and low software overhead transmission. FIFO size is 4 x 8 for both RX and TX direction. The UART has status registers that show the number of received characters available in the FIFO and various error conditions; in addition, it has the ability to generate interrupts based on these status bits.

An example of UART receiving or transmitting a single packet is shown in the following figure. This example shows 7-bit data (0x45), odd parity and two stop bits.

Figure 8-3. Example of UART RX or TX Packet