8.2 SPI Client Interface
The SPI client interface can be enabled by connecting the SDIO_SPI_CFG pin to VDDIO. This SPI interface is used to exchange the control and 802.11 data. The SPI is a full duplex client-synchronous serial interface that is available following reset when pin 10 (SDIO_SPI_CFG) is connected to VDDIO.
The SPI interface pin mapping configuration is provided in the following table.
| Pin Number | SPI Function |
|---|---|
| 10 | SDIO_SPI_CFG: Must be connected to VDDIO |
| 16 | SSN: Active-Low Client Select |
| 15 | MOSI: Serial Data Receive |
| 18 | SCK: Serial Clock |
| 17 | MISO: Serial Data Transmit |
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers between the serial host and other serial client devices. When the serial client is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the chip and also initiate DMA transfers.
The SPI SSN, MOSI, MISO and SCK pins of this module have internal programmable pull-up resistors. These resistors are programmed to be disabled. Otherwise, if any of the SPI pins are driven to a low level while this module is in the Low-Power Sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the module.
The SPI client interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. These modes are described in the following table.
| Mode | CPOL | CPHA |
|---|---|---|
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 2 | 1 | 0 |
| 3 | 1 | 1 |
The red lines in the following figure correspond to clock phase at 0 and the blue lines correspond to clock phase at 1.
