4.6.1 SPI Timing

The SPI timing is shown in the following figure.

Figure 4-1. SPI Timing Diagram (SPI MODE CPOL = 0, CPHA = 0)

The SPI client timing parameters are provided in the following table.

Table 4-6. SPI Client Timing Parameters(1)
ParameterSymbolMin.Max.Units
Clock Input Frequency(2)fSCK—48MHz
Clock Low Pulse WidthtWL4—ns
Clock High Pulse WidthtWH5—
Clock Rise TimetLH07
Clock Fall TimetHL07
TXD Output Delay(3)tODLY49 from SCK fall
RXD Input Setup TimetISU1—
RXD Input Hold TimetIHD5—
SSN Input Setup TimetSUSSN3—
SSN Input Hold TimetHDSSN5.5—
Note:
  1. Timing is applicable to all of the SPI modes.
  2. Maximum clock frequency specified is limited by the SPI client interface internal design; the actual maximum clock frequency can be lower and depends on the specific PCB layout.
  3. Timing is based on 15 pF output loading. Under all conditions, tLH + tWH + tHL + tWL must be less than or equal to 1/ fSCK.