36 Revision History

Revision A (April 2022)

This is the initial version of the document.

Revision B (May 2022)

This revision incorporates the following updates:

  • Sections:
    • Changed the first bullet in the Peripheral Features section to Three Quadrature Encoder Interfaces (QEIs).
    • Changed the sixth bullet in the Safety Features section to Flash OTP by ICSP™ Write Inhibit.
    • Updated 1. Device Overview and 2. Guidelines for Getting Started with High-Performance Digital Signal Processors.
    • Updated document title to High-Performance Digital Signal Controllers with High-Resolution PWM and CAN Flexible Data-Rate (CAN FD).
  • Tables:
    • Updated Table 13-1: External Input Availability, Table 34-6. DC Characteristics: Operating Current (IDD), Table 34-7. Idle Current (IIDLE), Table 34-8. DC Characteristics: Power-Down Current (IPD), Table 34-10. DC Characteristics: Watchdog Timer Delta Current (ΔIWDT), Table 34-16. I/O Pin Input Specifications, Table 35-6. DC Characteristics: Operating Current (IDD) and Table 35-9. DOZE Current (IDOZE).
    • Added Table 34-9. DOZE Current (IDOZE), Table 34-15. Op Amp Delta Current and Table 35-7: Idle Current (IIDLE).
    • Removed Table 34-22. Capacitive Loading Requirements on Output Pins, Table 34-41. Die Temperature Diode Specifications, Table 35-7. DC Characteristics: Operating Current (IDD) (Sleep), Table 35-8. DC Characteristics: Operating Current (IDD) (Run), Table 35-10. DC Characteristics: Idle Current (IIDLE) , Table 35-11. DC Characteristics: Idle Current (IIDLE) (Sleep) and Table 35-18. Internal LPRC Accuracy.
  • Registers:
    • Updated 13.4.4 ADC Control Register 2 High.
    • Added the following registers: CLC5GLSL-CLC8GLSL, CLC5GLSH-CLC8GLSH, CLC6CONL-CLC8CONL, CLC6CONH-CLC8CONH and CLC6SELL-CLC8SELL.
  • Figures
    • Updated Figure 1. 48-Pin TQFP/VQFN, Figure 2. 64-Pin TQFP, QFN, Figure 3. 80-Pin TQFP, Figure 4. 100-Pin TQFP, Figure 1-1. dsPIC33CK1024MP710 Family Block Diagram, Figure 13-1. ADC Module Block Diagram, Figure 13-2. Shared Core Block Diagramand Figure 34-1. Load Conditions for Device Timing Specifications.

Minor grammatical corrections and formatting changes throughout the document.

Revision C (April 2023)

This revision incorporates the following updates:

  • Sections:
    • Changed Functional Safety Support – ISO 26262/IEC 61508/IEC 60730 title and content.
    • Added new content to the first paragraph in 5.6.1 Flash Partition Swapping.
    • Added new paragraph to 12.2 Architecture Overview.
    • Added new paragraph to 30.6 Brown-out Reset (BOR).
    • Added note to 30.7 Dual Watchdog Timer (WDT).
  • Tables:
    • Updated Table 1. dsPIC33CK1024MP710 Motor Control/Power Supply Families with CAN FD, Table 2. dsPIC33CK1024MP710 Motor Control/Power Supply Families with No CAN FD, Table 5. 80-Pin TQFP, Table 8-3. Remappable Pin Inputs, Table 8-5. Remappable Output Pin Registers, Table 8-6. Output Selection for Remappable Pins (RPn), Table 33-3. Thermal Operating Conditions, Table 33-36. UARTx Module I/O Timing Requirements, Table 33-39. DACx Module Specifications and Table 34-19. DACx Module Specifications.
  • Registers:
    • Updated 3.5.29 Y Page Register, 7.7.1 Interrupt Request Flags Register 0, 7.7.14 Interrupt Enable Register 0, 9.11.1 Oscillator Control Register, 11.2.1 CAN Control Register Low, 12.6.8 Auxiliary Combinational Trigger Register Low, 12.6.9 Auxiliary Combinational Trigger Register High, 12.6.10 Auxiliary Combinatorial PWM Logic Control Register y, 12.6.19 Auxiliary PWM Generator xy PCI Register Low, 12.6.20 Auxiliary PWM Generator xy PCI Register High, 12.6.22 Auxiliary PWM Generator x Leading-Edge Blanking Register High, 14.4.4 DACx Control Low Register, 14.4.8 DAC Slope x Control Low Register, 22.6.1 CCPx Control 1 Low Register and 28.1.1 Deadman Timer Control Register.
    • Changes all instances of PWM, FSMINPER, PG, MPER, PGxPER, PGxPHASE, PGxCAP, PGxCON, PGxTRIG, PGxSTAT, PGxDCA in the Auxiliary PWM section to APWM, AFSMINPER, APG, AMPER, APGxPER, APGxPHASE, APGxCAP, APGxCON, APGxTRIG, APGxSTAT, APGxDCA.
  • Figures:
    • Updated Figure 11-1. CAN FD Module Block Diagram.

Revision D (August 2026)

This revision incorporates the following updates:

  • Sections:
    • Updated Timers/Output Compare/Input Capture, Referenced Sources, 2.4 ICSP Pins, 2.6 External Oscillator Layout Guidance, 3.3 Data Space Addressing, 5.3 Error Correcting Code (ECC), 5.4 ECC Fault Injection, 6. Resets, 6.1.1 Key Resources, 7.1 Interrupt Vector Table, 10.1.1 Source and Destination, 10.1.3 Trigger Source, 10.1.5 Addressing Modes, 10.2.2 DMA Registers, 12.4 PWM4H/L Output on Peripheral Pin Select, 14. High-Speed Analog Comparator with Slope Compensation DAC, 15. Quadrature Encoder Interface (QEI), 21. Timer1, 22. Capture/Compare/PWM/Timer Modules (SCCP), 22.1 Time Base Generator, 30.9 In-Circuit Debugger and Product Identification System.
    • Added 5.6.1 Activating Flash OTP by ICSP Write Inhibit.
  • Tables:
    • Updated Table 1-1. Pinout I/O Descriptions, Table 7-2. Interrupt Vector Details, Table 10-1. DMA Channel Trigger Sources CHSEL[6:0] Trigger (Interrupt), Table 22-5. Synchronization Sources, Table 33-5. Operating Voltage Specifications, Table 33-6. DC Characteristics: Operating Current (IDD), Table 33-8. DC Characteristics: Power-Down Current (IPD), Table 33-17. I/O Pin Input Injection Current Specifications, Table 33-24. Internal FRC Accuracy, Table 33-32. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Requirements, Table 33-35. I2Cx Bus Data Timing Requirements (Client Mode), Table 33-37. ADC Module Specifications, Table 34-5. Operating Voltage Specifications and Table 34-6. DC Characteristics: Operating Current (IDD).
    • Added Table 33-25. Internal LPRC Accuracy and Table 33-40. Die Temperature Diode Specifications.
  • Registers:
    • Updated 3.5.12 Data Space Write Page Register, 4.3.4 MBIST Control Register, 5.7.12 ECC System Status Display Register High, 6.1.2 Reset Control Register, 7.7.1 Interrupt Request Flags Register 0, 7.7.2 Interrupt Request Flags Register 1, 7.7.3 Interrupt Request Flags Register 2, 7.7.4 Interrupt Request Flags Register 3, 7.7.5 Interrupt Request Flags Register 4, 7.7.6 Interrupt Request Flags Register 5, 7.7.7 Interrupt Request Flags Register 6, 7.7.8 Interrupt Request Flags Register 7, 7.7.9 Interrupt Request Flags Register 8, 7.7.10 Interrupt Request Flags Register 9, 7.7.11 Interrupt Request Flags Register 10, 7.7.12 Interrupt Request Flags Register 11, 7.7.13 Interrupt Request Flags Register 12, 7.7.21 Interrupt Enable Register 7, 7.7.24 Interrupt Enable Register 10, 7.7.26 Interrupt Enable Register 12, 7.7.46 Interrupt Priority Register 19, 7.7.47 Interrupt Priority Register 20, 7.7.49 Interrupt Priority Register 22, 7.7.55 Interrupt Priority Register 28, 7.7.58 Interrupt Priority Register 31, 7.7.61 Interrupt Priority Register 34, 7.7.63. Interrupt Priority Register 35, 7.7.72. Interrupt Priority Register 46, 7.7.74 Interrupt Priority Register 48, 8.2.2.1 Analog Select for PORTx Register, 8.2.2.2 Output Enable for PORTx Register, 8.2.2.3 Input Data for PORTx Register, 8.2.2.4 Output Data for PORTx Register, 9.11.5 PLL Output Divider Register, 9.11.6 Auxiliary Clock Control Register, 10.2.3.3 DMA Low Address Limit Register, 10.2.3.4 DMA High Address Limit Register, 10.2.3.8 DMA Data Destination Address Pointer Channel n Register, 11.2.1. CAN Control Register Low, 11.2.2. CAN Control Register High, 11.2.3. CAN Nominal Bit Time Configuration Register Low, 11.2.4. CAN Nominal Bit Time Configuration Register High, 11.2.5. CAN Data Bit Time Configuration Register Low, 11.2.6. CAN Data Bit Time Configuration Register High, 11.2.7. CAN Transmitter Delay Compensation Register Low, 11.2.8. CAN Transmitter Delay Compensation Register High, 11.2.9. CAN Time Base Counter Register Low, 11.2.10. CAN Time Base Counter Register High, 11.2.11. CAN Timestamp Control Register Low, 11.2.12. CAN Timestamp Control Register High, 11.2.13. CAN Interrupt Code Register Low, 11.2.14. CAN Interrupt Code Register High, 11.2.15. CAN Interrupt Register Low, 11.2.16. CAN Interrupt Register High, 11.2.17. CAN Receive Interrupt Status Register Low, 11.2.18. CAN Receive Interrupt Status Register High, 11.2.19. CAN Transmit Interrupt Status Register Low, 11.2.20. CAN Transmit Interrupt Status Register High, 11.2.21. CAN Receive Overflow Interrupt Status Register Low, 11.2.22. CAN Receive Overflow Interrupt Status Register High, 11.2.23. CAN Transmit Attempt Interrupt Status Register Low, 11.2.33. CANx Transmit Event FIFO Control Register Low, 11.2.35. CANx Transmit Event FIFO Status Register, 11.2.36. CANx Transmit Event FIFO User Address Register Low, 11.2.40. CANx Transmit Queue Control Register Low, 11.2.43. CAN Transmit Queue User Address Register Low, 11.2.44. CAN Transmit Queue User Address Register High, 11.2.45. CAN2 FIFO Control Register x Low, 11.2.46. CAN2 FIFO Control Register x High (x = 1 to 7), 11.2.47. CAN FIFO Status Register x, 11.2.48. CAN FIFO User Address Register x Low, 11.2.49. CAN FIFO User Address Register x High, 11.2.50. CAN2 Filter Control Register x Low, 11.2.51. CAN2 Filter Control Register x High, 12.6.13 Auxiliary PWM Generator x Control Register High, 12.6.14 Auxiliary PWM Generator x Status Register, 12.6.15 Auxiliary PWM Generator x I/O Control Register Low, 12.6.17. Auxiliary APWM Generator x Event Register Low, 12.6.32 Auxiliary PWM Generator x Capture Register, 12.6.45 PWM Generator x Control Register High, 12.6.46 PWM Generator x Status Register, 12.6.47 PWM Generator x I/O Control Register Low, 12.6.49 PWM Generator x Event Register Low, 12.6.51 PWM Generator x PCI Register Low, 12.6.64 PWM Generator x Capture Register, 13.4.5 ADC Control Register 3 Low, 13.4.15 ADC Data Ready Status Register Low, 13.4.16 ADC Data Ready Status Register High, 13.4.43 Dedicated ADC Core x Control Register High, 13.4.46 ADC Early Interrupt Status Register Low, 13.4.47 ADC Early Interrupt Status Register High, 14.4.1 DAC Control 1 Low Register, 14.4.4 DACx Control Low Register, 15.1.1 QEIx Control Register, 17.1.2 SPI3 Buffer Register High, 17.1.12 SPIx Baud Rate Generator Register Low, 18. Inter-Integrated Circuit (I2C), 19. Parallel Main Port (PMP), 19.1.4 PMP Address Register, 19.1.12 PMP Read Address Register, 20.3.1 SENTx Control Register 1, 20.3.1 SENTx Control Register 1, 20.3.2 SENTx Control Register 2, 20.3.3 SENTx Control Register 3, 21.1.1 Timer1 Control Register, 21.1.3 Period Register 1, 22.6.4 CCPx Control 2 High Register, 22.6.12. CCPx Period Low Register, 22.6.13. CCPx Period High Register, 22.6.14. CCPx Primary Compare Register (Timer/Compare Modes Only), 22.6.15. CCPx Secondary Compare Register (Timer/Compare Modes Only), 23.1.3. CLCx Input MUX Select Register, 23.1.4. CLCy Input MUX Select Register, 24.2.1 PTG Control/Status Low Register, 24.2.3 PTG Broadcast Trigger Enable Register Low, 24.2.4 PTG Broadcast Trigger Enable Low Register, 24.2.14 PTG Step Queue x Pointer Register (x = 0-15), 25.1.3 CRC XOR Polynomial Register, Low Byte, 26.1.2 Current Bias Generator 50 μA Current Source Control Low Register, 26.1.3 Current Bias Generator 50 μA Current Source Control High Register, 28.1.8 DMT Post-Configure Count Status Register Low, 28.1.9 DMT Post-Configure Count Status Register High, 28.1.10 DMT Post-Configure Interval Status Register Low, 28.1.11 DMT Post-Configure Interval Status Register High, 29.6.1 Peripheral Module Disable Control Register, 29.6.2 Peripheral Module Disable 1 Register, 29.6.3. Peripheral Module Disable 2 Register, 29.6.7 Peripheral Module Disable 7 Register, 30.2.6 FWDT Configuration Register, 30.7 Dual Watchdog Timer (WDT) and 30.7.1 Watchdog Timer Control Register Low.
    • Removed Interrupt Priority Register 40 and 7.7.1 Interrupt Request Flags Register 0.
    • Added DMA High and Low Address Extended Limit Register, DMA Data Source and Destination Extended Address Pointer Channel 0-7 Registers, CRC Data Register Low, CRC Data Register High,CRC Result Register Low, CRC Result Register High,
    • Added all PWM Generator x PCI Registers, Auxiliary PWM Generator x PCI Registers and 22.6.6. CCP9 Control 3 Low Register,
  • Figures:
    • Updated Figure 1. 48-Pin TQFP/VQFN, Figure 2. 64-Pin TQFP, QFN, Figure 3. 80-Pin TQFP, Figure 4. 100-Pin TQFP, Figure 4-6. Data Memory Map for dsPIC33CKXXXXMPXXX Devices, Figure 7-2. dsPIC33CK1024MP710 Alternate Interrupt Vector Table, Figure 17-4. SPIx Main Connection (Enhanced Buffer Modes), Figure 19-1. PMP Module Pinout and Connections to External Devices and Figure 22-3. Output Compare x Block Diagram.