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PIC16F18054/55/74/75 Full-Featured, 28/40-Pin Microcontrollers PIC16F18054/55/74/75
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Introduction
PIC16F180
Family Types
Core Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
Block Diagram
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC16F180
Microcontrollers
4.1
Basic Connection Requirements
4.2
Power Supply Pins
4.3
Master Clear (
MCLR
) Pin
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
4.5
Unused I/Os
5
Register and Bit Naming Conventions
5.1
Register Names
5.2
Bit Names
5.3
Register and Bit Naming Exceptions
6
Register Legend
7
Enhanced Mid-Range CPU
7.1
Automatic Interrupt Context Saving
7.2
16
-Level Stack with Overflow and Underflow
7.3
File Select Registers
7.4
Instruction Set
8
Device Configuration
8.1
Configuration Words
8.2
Code Protection
8.3
Write Protection
8.4
User ID
8.5
Device ID and Revision ID
8.6
Register Definitions: Configuration Settings
8.7
Register Definitions: Device ID and Revision ID
9
Memory Organization
9.1
Program Memory Organization
9.2
Data Memory Organization
9.3
STATUS Register
9.4
PCL and PCLATH
9.5
Stack
9.6
Indirect Addressing
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
Resets
10.1
Power-on Reset (POR)
10.2
Brown-out Reset (BOR)
10.3
MCLR
Reset
10.4
Watchdog Timer (WDT) Reset
10.5
RESET
Instruction
10.6
Stack Overflow/Underflow Reset
10.7
Power-Up Timer (PWRT)
10.8
Start-Up Sequence
10.9
Memory Execution Violation
10.10
Determining the Cause of a Reset
10.11
Power Control (PCONx) Register
10.12
Register Definitions: Power Control
10.13
Register Summary - Power Control
11
OSC - Oscillator Module
11.1
Clock Source Types
11.2
Active Clock Tuning (ACT)
11.3
Register Definitions: Oscillator Module
11.4
Register Summary - Oscillator Module
12
INT - Interrupts
12.1
Overview
12.2
INTCON Register
12.3
PIE Registers
12.4
PIR Registers
12.5
Operation
12.6
Interrupt Latency
12.7
Interrupts During Sleep
12.8
INT Pin
12.9
Automatic Context Saving
12.10
Register Definitions: Interrupt Control
12.11
Register Summary - Interrupt Control
13
Sleep Mode
13.1
Sleep Mode Operation
14
WDT - Watchdog Timer
14.1
Selectable Clock Sources
14.2
WDT Operating Modes
14.3
WDT Time-Out Period
14.4
Clearing the WDT
14.5
WDT Operation During Sleep
14.6
Register Definitions: WDT Control
14.7
Register Summary - WDT Control
15
NVM - Nonvolatile Memory Control
15.1
Program Flash Memory (PFM)
15.2
Data Flash Memory (DFM)
15.3
Register Definitions: Nonvolatile Memory Control
15.4
Register Summary - NVM Control
16
I/O Ports
16.1
Overview
16.2
PORTx - Data Register
16.3
LATx - Output Latch
16.4
TRISx - Direction Control
16.5
ANSELx - Analog Control
16.6
WPUx - Weak Pull-Up Control
16.7
INLVLx - Input Threshold Control
16.8
SLRCONx - Slew Rate Control
16.9
ODCONx - Open-Drain Control
16.10
Edge Selectable Interrupt-on-Change
16.11
I
2
C Pad Control
16.12
I/O Priorities
16.13
MCLR
/V
PP
/RE3
Pin
16.14
Register Definitions: Port Control
16.15
Register Summary - IO Ports
17
IOC - Interrupt-on-Change
17.1
Overview
17.2
Enabling the Module
17.3
Individual Pin Configuration
17.4
Interrupt Flags
17.5
Clearing Interrupt Flags
17.6
Operation in Sleep
17.7
Register Definitions: Interrupt-on-Change Control
17.8
Register Summary - Interrupt-on-Change
18
PPS - Peripheral Pin Select Module
18.1
Overview
18.2
PPS Inputs
18.3
PPS Outputs
18.4
Bidirectional Pins
18.5
PPS Lock
18.6
Operation During Sleep
18.7
Effects of a Reset
18.8
Register Definitions: Peripheral Pin Select (PPS)
18.9
Register Summary - Peripheral Pin Select Module
19
CRC - Cyclic Redundancy Check Module
19.1
Module Overview
19.2
Polynomial Implementation
19.3
Data Source
19.4
CRC Check Value
19.5
CRC Interrupt
19.6
Operation During Sleep
19.7
Configuring the CRC Module
19.8
Register Definitions: CRC Control
19.9
Register Summary - CRC
20
TMR0 - Timer0 Module
20.1
Timer0 Operation
20.2
Clock Selection
20.3
Timer0 Output and Interrupt
20.4
Operation During Sleep
20.5
Register Definitions: Timer0 Control
20.6
Register Summary - Timer0
21
TMR1 - Timer1 Module with Gate Control
21.1
Timer1 Operation
21.2
Clock Source Selection
21.3
Timer1 Prescaler
21.4
Secondary Oscillator
21.5
Timer1 Operation in Asynchronous Counter Mode
21.6
Timer1 16-Bit Read/Write Mode
21.7
Timer1 Gate
21.8
Timer1 Interrupt
21.9
Timer1 Operation During Sleep
21.10
CCP Capture/Compare Time Base
21.11
CCP Special Event Trigger
21.12
Peripheral Module Disable
21.13
Register Definitions: Timer1 Control
21.14
Register Summary - Timer1
22
TMR2 - Timer2 Module
22.1
Timer2 Operation
22.2
Timer2 Output
22.3
External Reset Sources
22.4
Timer2 Interrupt
22.5
PSYNC Bit
22.6
CSYNC Bit
22.7
Operating Modes
22.8
Operation Examples
22.9
Timer2 Operation During Sleep
22.10
Register Definitions: Timer2 Control
22.11
Register Summary - Timer2
23
NCO - Numerically Controlled Oscillator Module
23.1
NCO Operation
23.2
Fixed Duty Cycle Mode
23.3
Pulse Frequency Mode
23.4
Output Polarity Control
23.5
Interrupts
23.6
Effects of a Reset
23.7
Operation in Sleep
23.8
Register Definitions: NCO
23.9
Register Summary - NCO
24
CWG - Complementary Waveform Generator Module
24.1
Fundamental Operation
24.2
Operating Modes
24.3
Clock Source
24.4
Selectable Input Sources
24.5
Output Control
24.6
Dead-Band Control
24.7
Rising Edge and Reverse Dead Band
24.8
Falling Edge and Forward Dead Band
24.9
Dead-Band Jitter
24.10
Auto-Shutdown
24.11
Auto-Shutdown Restart
24.12
Operation During Sleep
24.13
Configuring the CWG
24.14
Register Definitions: CWG Control
24.15
Register Summary - CWG
25
CCP - Capture/Compare/PWM Module
25.1
CCP Module Configuration
25.2
Capture Mode
25.3
Compare Mode
25.4
PWM Overview
25.5
Register Definitions: CCP Control
25.6
Register Summary - CCP Control
26
Capture, Compare, and PWM Timers Selection
26.1
Register Definitions: Capture, Compare, and PWM Timers Selection
26.2
Register Summary - Capture, Compare, and PWM Timers Selection
27
PWM - Pulse-Width Modulation
27.1
Fundamental Operation
27.2
PWM Output Polarity
27.3
PWM Period
27.4
PWM Duty Cycle
27.5
PWM Resolution
27.6
Operation in Sleep Mode
27.7
Changes in System Clock Frequency
27.8
Effects of Reset
27.9
Setup for PWM Operation Using PWMx Output Pins
27.10
Setup for PWM Operation to Other Device Peripherals
27.11
Register Definitions: PWM Control
27.12
Register Summary - PWM
28
PWM Timers Selection
28.1
Register Definitions: Capture, Compare, and PWM Timers Selection
28.2
Register Summary - Capture, Compare, and PWM Timers Selection
29
CLC - Configurable Logic Cell
29.1
CLC Setup
29.2
CLC Interrupts
29.3
Effects of a Reset
29.4
Output Mirror Copies
29.5
Operation During Sleep
29.6
CLC Setup Steps
29.7
Register Overlay
29.8
Register Definitions: Configurable Logic Cell
29.9
Register Summary - CLC Control
30
MSSP - Host Synchronous Serial Port Module
30.1
SPI Mode Overview
30.2
I
2
C Mode Overview
30.3
Baud Rate Generator
30.4
Register Definitions: MSSP Control
30.5
Register Summary - MSSP Control
31
EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
31.1
EUSART Asynchronous Mode
31.2
Clock Accuracy with Asynchronous Operation
31.3
EUSART Baud Rate Generator (BRG)
31.4
EUSART Synchronous Mode
31.5
EUSART Operation During Sleep
31.6
Register Definitions: EUSART Control
31.7
Register Summary - EUSART
32
ADC - Analog-to-Digital Converter with Computation Module
32.1
ADC Configuration
32.2
ADC Operation
32.3
ADC Acquisition Requirements
32.4
Computation Operation
32.5
Register Definitions: ADC Control
32.6
Register Summary - ADC
33
DAC - Digital-to-Analog Converter Module
33.1
Output Voltage Selection
33.2
Ratiometric Output Level
33.3
Buffered DAC Output Range Selection
33.4
Operation During Sleep
33.5
Effects of a Reset
33.6
Register Definitions: DAC Control
33.7
Register Summary - DAC
34
CMP - Comparator Module
34.1
Comparator Overview
34.2
Comparator Control
34.3
Comparator Output Synchronization
34.4
Comparator Hysteresis
34.5
Comparator Interrupt
34.6
Comparator Positive Input Selection
34.7
Comparator Negative Input Selection
34.8
Comparator Response Time
34.9
Analog Input Connection Considerations
34.10
Operation in Sleep Mode
34.11
ADC Auto-Trigger Source
34.12
Register Definitions: Comparator Control
34.13
Register Summary - Comparator
35
FVR - Fixed Voltage Reference
35.1
Independent Gain Amplifiers
35.2
FVR Stabilization Period
35.3
Register Definitions: FVR
35.4
Register Summary - FVR
36
Temperature Indicator Module
36.1
Module Operation
36.2
Temperature Calculation
36.3
ADC Acquisition Time
36.4
Register Definitions: Temperature Indicator
36.5
Register Summary - Temperature Indicator
37
ZCD - Zero-Cross Detection Module
37.1
External Resistor Selection
37.2
ZCD Logic Output
37.3
ZCD Logic Polarity
37.4
ZCD Interrupts
37.5
Correction for Z
CPINV
Offset
37.6
Handling V
PEAK
Variations
37.7
Operation During Sleep
37.8
Effects of a Reset
37.9
Disabling the ZCD Module
37.10
Register Definitions: ZCD Control
37.11
Register Summary - ZCD
38
Charge Pump
38.1
Manually Enabled
38.2
Automatically Enabled
38.3
Disabled
38.4
Charge Pump Oscillator
38.5
Charge Pump Threshold
38.6
Charge Pump Ready
38.7
Register Definitions: Charge Pump
38.8
Register Summary - Charge Pump
39
Instruction Set Summary
39.1
Read-Modify-Write Operations
39.2
Standard Instruction Set
40
ICSP™ - In-Circuit Serial Programming™
40.1
High-Voltage Programming Entry Mode
40.2
Low-Voltage Programming Entry Mode
40.3
Common Programming Interfaces
41
Register Summary
42
Electrical Specifications
42.1
Absolute Maximum Ratings
(†)
42.2
Standard Operating Conditions
42.3
DC Characteristics
42.4
AC Characteristics
43
DC and AC Characteristics Graphs and Tables
44
Packaging Information
44.1
Package Details
45
Appendix A: Revision History
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