14.2.1.2.4 PLL_ON - PLL State

Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first, unless the AVREG is already switched on (TRX_CTRL_2.TRX_OFF_AVDD_EN). After the voltage regulator has been settled, the PLL frequency synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by the CHANNEL bits in the PHY_CC_CCA register ( PHY_CC_CCA.CHANNEL) or the CC_NUMBER bits in the CC_CTRL_0 register (CC_CTRL_0.CC_NUMBER) and the CC_BAND bits in the CC_CTRL_1 register (CC_CTRL_1.CC_BAND), a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK).

If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately. If the PLL has not been settled before the state change nevertheless takes place. Even if the TRX_STATUS bits in the TRX_STATUS register (TRX_STATUS.TRX_STATUS) indicates RX_ON, actual frame reception can only start once the PLL has locked.

The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.