29.16.2 PMC System Clock Disable Register
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | PMC_SCDR |
| Offset: | 0x0004 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| QSPICLK | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCK1 | PCK0 | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UHP | DDRCK | ||||||||
| Access | W | W | |||||||
| Reset | – | – |
Bit 19 – QSPICLK QSPI 2x Clock Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the QSPI 2x clock. |
Bits 8, 9 – PCKx Programmable Clock x Output Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the corresponding Programmable Clock output. |
Bit 6 – UHP USB Host OHCI Clocks Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the UHP48M and UHP12M OHCI clocks. |
Bit 2 – DDRCK MPDDRC/SDRAMC Clock Disable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Disables the MPDDRC or SDRAMC clock. |