29.16.1 PMC System Clock Enable Register

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

Name: PMC_SCER
Offset: 0x0000
Reset: –
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     QSPICLK    
Access W 
Reset – 
Bit 15141312111098 
       PCK1PCK0 
Access WW 
Reset –– 
Bit 76543210 
  UHP   DDRCK   
Access WW 
Reset –– 

Bit 19 – QSPICLK QSPI 2x Clock Enable

ValueDescription
0 No effect.
1 Enables the QSPI 2x clock.

Bits 8, 9 – PCKx Programmable Clock x Output Enable

ValueDescription
0 No effect.
1 Enables the corresponding Programmable Clock output.

Bit 6 – UHP USB Host OHCI Clocks Enable

ValueDescription
0 No effect.
1 Enables the UHP48M and UHP12M OHCI clocks.

Bit 2 – DDRCK MPDDRC/SDRAMC Clock Enable

ValueDescription
0 No effect.
1 Enables the MPDDRC or SDRAMC clock.