29.16.11 PMC CPU Clock Register

This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.

The CSS, PRES and MDIV fields cannot be modified simultaneously. If more than one field modification is required, proceed sequentially: modify the first field and wait for PMC_SR.MCKRDY high, then modify the second field and wait for PMC_SR.MCKRDY high, etc.

Name:	PMC_CPU_CKR
Offset:	0x0028
Reset:	0x00000001
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
						MDIV[2:0]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	7	6	5	4	3	2	1	0
		PRES[2:0]					CSS[1:0]
Access		R/W	R/W	R/W			R/W	R/W
Reset		0	0	0			0	1

Bits 10:8 – MDIV[2:0] MCK Division

Value	Name	Description
0	EQ_PCK	MCK is FCLK divided by 1. MCK_2X is FCLK divided by 1.
1	PCK_DIV2	MCK is FCLK divided by 2. MCK_2X is FCLK divided by 1.
2	PCK_DIV4	MCK is FCLK divided by 4. MCK_2X is FCLK divided by 2.
3	PCK_DIV3	MCK is FCLK divided by 3. MCK_2X is FCLK divided by 1.5.

Bits 6:4 – PRES[2:0] Processor Clock Prescaler

Value	Name	Description
0	CLK_1	Selected clock
1	CLK_2	Selected clock divided by 2
2	CLK_4	Selected clock divided by 4
3	CLK_8	Selected clock divided by 8
4	CLK_16	Selected clock divided by 16
5	CLK_32	Selected clock divided by 32
6	CLK_64	Selected clock divided by 64
7	CLK_3	Selected clock divided by 3

Bits 1:0 – CSS[1:0] MCK Source Selection

Value	Name	Description
0	SLOW_CLK	MD_SLCK is selected.
1	MAIN_CLK	MAINCK is selected.
2	PLLACK	PLLACK is selected.
3	UPLLCK	UPLLCK is selected.