29.16.3 PMC System Clock Status Register
| Name: | PMC_SCSR |
| Offset: | 0x0008 |
| Reset: | 0x00000001 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| QSPICLK | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCK1 | PCK0 | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| UHP | DDRCK | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bit 19 – QSPICLK QSPI 2x Clock Status
| Value | Description |
|---|---|
| 0 | The QSPI 2x clock is disabled. |
| 1 | The QSPI 2x clock is enabled. |
Bits 8, 9 – PCKx Programmable Clock x Output Status
| Value | Description |
|---|---|
| 0 | The corresponding Programmable Clock output is disabled. |
| 1 | The corresponding Programmable Clock output is enabled. |
Bit 6 – UHP USB Host OHCI Clocks Status
| Value | Description |
|---|---|
| 0 | The UHP48M and UHP12M OHCI clocks are disabled. |
| 1 | The UHP48M and UHP12M OHCI clocks are enabled. |
Bit 2 – DDRCK MPDDRC/SDRAMC Clock Status
| Value | Description |
|---|---|
| 0 | The MPDDRC or SDRAMC clock is disabled. |
| 1 | The MPDDRC or SDRAMC clock is enabled. |